Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
linux
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
Kirill Smelkov
linux
Commits
671e9696
Commit
671e9696
authored
Nov 08, 2015
by
Ben Skeggs
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
drm/nouveau/nvif: split out device control interface definitions
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
8ed1730c
Changes
4
Hide whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
49 additions
and
49 deletions
+49
-49
drivers/gpu/drm/nouveau/include/nvif/class.h
drivers/gpu/drm/nouveau/include/nvif/class.h
+1
-49
drivers/gpu/drm/nouveau/include/nvif/if0001.h
drivers/gpu/drm/nouveau/include/nvif/if0001.h
+46
-0
drivers/gpu/drm/nouveau/nouveau_sysfs.c
drivers/gpu/drm/nouveau/nouveau_sysfs.c
+1
-0
drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
+1
-0
No files found.
drivers/gpu/drm/nouveau/include/nvif/class.h
View file @
671e9696
...
...
@@ -2,7 +2,7 @@
#define __NVIF_CLASS_H__
/* these class numbers are made up by us, and not nvidia-assigned */
#define NVIF_CLASS_CONTROL
-1
#define NVIF_CLASS_CONTROL
/* if0001.h */
-1
#define NVIF_CLASS_PERFMON -2
#define NVIF_CLASS_PERFDOM -3
#define NVIF_CLASS_SW_NV04
/* if0004.h */
-4
...
...
@@ -341,52 +341,4 @@ struct nvif_perfdom_read_v0 {
__u32
clk
;
__u8
pad04
[
4
];
};
/*******************************************************************************
* device control
******************************************************************************/
#define NVIF_CONTROL_PSTATE_INFO 0x00
#define NVIF_CONTROL_PSTATE_ATTR 0x01
#define NVIF_CONTROL_PSTATE_USER 0x02
struct
nvif_control_pstate_info_v0
{
__u8
version
;
__u8
count
;
/* out: number of power states */
#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
__s8
ustate_ac
;
/* out: target pstate index */
__s8
ustate_dc
;
/* out: target pstate index */
__s8
pwrsrc
;
/* out: current power source */
#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
__s8
pstate
;
/* out: current pstate index */
__u8
pad06
[
2
];
};
struct
nvif_control_pstate_attr_v0
{
__u8
version
;
#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
__s8
state
;
/* in: index of pstate to query
* out: pstate identifier
*/
__u8
index
;
/* in: index of attribute to query
* out: index of next attribute, or 0 if no more
*/
__u8
pad03
[
5
];
__u32
min
;
__u32
max
;
char
name
[
32
];
char
unit
[
16
];
};
struct
nvif_control_pstate_user_v0
{
__u8
version
;
#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
__s8
ustate
;
/* in: pstate identifier */
__s8
pwrsrc
;
/* in: target power source */
__u8
pad03
[
5
];
};
#endif
drivers/gpu/drm/nouveau/include/nvif/if0001.h
0 → 100644
View file @
671e9696
#ifndef __NVIF_IF0001_H__
#define __NVIF_IF0001_H__
#define NVIF_CONTROL_PSTATE_INFO 0x00
#define NVIF_CONTROL_PSTATE_ATTR 0x01
#define NVIF_CONTROL_PSTATE_USER 0x02
struct
nvif_control_pstate_info_v0
{
__u8
version
;
__u8
count
;
/* out: number of power states */
#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
__s8
ustate_ac
;
/* out: target pstate index */
__s8
ustate_dc
;
/* out: target pstate index */
__s8
pwrsrc
;
/* out: current power source */
#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
__s8
pstate
;
/* out: current pstate index */
__u8
pad06
[
2
];
};
struct
nvif_control_pstate_attr_v0
{
__u8
version
;
#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
__s8
state
;
/* in: index of pstate to query
* out: pstate identifier
*/
__u8
index
;
/* in: index of attribute to query
* out: index of next attribute, or 0 if no more
*/
__u8
pad03
[
5
];
__u32
min
;
__u32
max
;
char
name
[
32
];
char
unit
[
16
];
};
struct
nvif_control_pstate_user_v0
{
__u8
version
;
#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
__s8
ustate
;
/* in: pstate identifier */
__s8
pwrsrc
;
/* in: target power source */
__u8
pad03
[
5
];
};
#endif
drivers/gpu/drm/nouveau/nouveau_sysfs.c
View file @
671e9696
...
...
@@ -24,6 +24,7 @@
#include <nvif/os.h>
#include <nvif/class.h>
#include <nvif/if0001.h>
#include <nvif/ioctl.h>
#include "nouveau_sysfs.h"
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
View file @
671e9696
...
...
@@ -27,6 +27,7 @@
#include <subdev/clk.h>
#include <nvif/class.h>
#include <nvif/if0001.h>
#include <nvif/ioctl.h>
#include <nvif/unpack.h>
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment