Commit 67e45621 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'riscv-for-linus-5.7-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:
 "A handful of build fixes, all found by Huawei's autobuilder.

  None of these patches should have any functional impact on kernels
  that build, and they're mostly related to various features
  intermingling with !MMU.

  While some of these might be better hoisted to generic code, it seems
  better to have the simple fixes in the meanwhile.

  As far as I know these are the only outstanding patches for 5.7"

* tag 'riscv-for-linus-5.7-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: mmiowb: Fix implicit declaration of function 'smp_processor_id'
  riscv: pgtable: Fix __kernel_map_pages build error if NOMMU
  riscv: Make SYS_SUPPORTS_HUGETLBFS depends on MMU
  riscv: Disable ARCH_HAS_DEBUG_VIRTUAL if NOMMU
  riscv: Add pgprot_writecombine/device and PAGE_SHARED defination if NOMMU
  riscv: stacktrace: Fix undefined reference to `walk_stackframe'
  riscv: Fix unmet direct dependencies built based on SOC_VIRT
  riscv: perf: RISCV_BASE_PMU should be independent
  riscv: perf_event: Make some funciton static
parents 01d8a748 ed1ed4c0
...@@ -54,7 +54,7 @@ config RISCV ...@@ -54,7 +54,7 @@ config RISCV
select GENERIC_ARCH_TOPOLOGY if SMP select GENERIC_ARCH_TOPOLOGY if SMP
select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_PTE_SPECIAL
select ARCH_HAS_MMIOWB select ARCH_HAS_MMIOWB
select ARCH_HAS_DEBUG_VIRTUAL select ARCH_HAS_DEBUG_VIRTUAL if MMU
select HAVE_EBPF_JIT if MMU select HAVE_EBPF_JIT if MMU
select EDAC_SUPPORT select EDAC_SUPPORT
select ARCH_HAS_GIGANTIC_PAGE select ARCH_HAS_GIGANTIC_PAGE
...@@ -136,6 +136,7 @@ config ARCH_SUPPORTS_DEBUG_PAGEALLOC ...@@ -136,6 +136,7 @@ config ARCH_SUPPORTS_DEBUG_PAGEALLOC
def_bool y def_bool y
config SYS_SUPPORTS_HUGETLBFS config SYS_SUPPORTS_HUGETLBFS
depends on MMU
def_bool y def_bool y
config STACKTRACE_SUPPORT config STACKTRACE_SUPPORT
......
...@@ -11,14 +11,15 @@ config SOC_SIFIVE ...@@ -11,14 +11,15 @@ config SOC_SIFIVE
This enables support for SiFive SoC platform hardware. This enables support for SiFive SoC platform hardware.
config SOC_VIRT config SOC_VIRT
bool "QEMU Virt Machine" bool "QEMU Virt Machine"
select POWER_RESET_SYSCON select POWER_RESET
select POWER_RESET_SYSCON_POWEROFF select POWER_RESET_SYSCON
select GOLDFISH select POWER_RESET_SYSCON_POWEROFF
select RTC_DRV_GOLDFISH select GOLDFISH
select SIFIVE_PLIC select RTC_DRV_GOLDFISH if RTC_CLASS
help select SIFIVE_PLIC
This enables support for QEMU Virt Machine. help
This enables support for QEMU Virt Machine.
config SOC_KENDRYTE config SOC_KENDRYTE
bool "Kendryte K210 SoC" bool "Kendryte K210 SoC"
......
...@@ -16,6 +16,8 @@ ...@@ -16,6 +16,8 @@
#ifndef CONFIG_MMU #ifndef CONFIG_MMU
#define pgprot_noncached(x) (x) #define pgprot_noncached(x) (x)
#define pgprot_writecombine(x) (x)
#define pgprot_device(x) (x)
#endif /* CONFIG_MMU */ #endif /* CONFIG_MMU */
/* Generic IO read/write. These perform native-endian accesses. */ /* Generic IO read/write. These perform native-endian accesses. */
......
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
*/ */
#define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory"); #define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory");
#include <linux/smp.h>
#include <asm-generic/mmiowb.h> #include <asm-generic/mmiowb.h>
#endif /* _ASM_RISCV_MMIOWB_H */ #endif /* _ASM_RISCV_MMIOWB_H */
...@@ -12,19 +12,14 @@ ...@@ -12,19 +12,14 @@
#include <linux/ptrace.h> #include <linux/ptrace.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#ifdef CONFIG_RISCV_BASE_PMU
#define RISCV_BASE_COUNTERS 2 #define RISCV_BASE_COUNTERS 2
/* /*
* The RISCV_MAX_COUNTERS parameter should be specified. * The RISCV_MAX_COUNTERS parameter should be specified.
*/ */
#ifdef CONFIG_RISCV_BASE_PMU
#define RISCV_MAX_COUNTERS 2 #define RISCV_MAX_COUNTERS 2
#endif
#ifndef RISCV_MAX_COUNTERS
#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU."
#endif
/* /*
* These are the indexes of bits in counteren register *minus* 1, * These are the indexes of bits in counteren register *minus* 1,
...@@ -82,6 +77,7 @@ struct riscv_pmu { ...@@ -82,6 +77,7 @@ struct riscv_pmu {
int irq; int irq;
}; };
#endif
#ifdef CONFIG_PERF_EVENTS #ifdef CONFIG_PERF_EVENTS
#define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs
#endif #endif
......
...@@ -470,12 +470,15 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, ...@@ -470,12 +470,15 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
#else /* CONFIG_MMU */ #else /* CONFIG_MMU */
#define PAGE_SHARED __pgprot(0)
#define PAGE_KERNEL __pgprot(0) #define PAGE_KERNEL __pgprot(0)
#define swapper_pg_dir NULL #define swapper_pg_dir NULL
#define VMALLOC_START 0 #define VMALLOC_START 0
#define TASK_SIZE 0xffffffffUL #define TASK_SIZE 0xffffffffUL
static inline void __kernel_map_pages(struct page *page, int numpages, int enable) {}
#endif /* !CONFIG_MMU */ #endif /* !CONFIG_MMU */
#define kern_addr_valid(addr) (1) /* FIXME */ #define kern_addr_valid(addr) (1) /* FIXME */
......
...@@ -43,7 +43,7 @@ obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o ...@@ -43,7 +43,7 @@ obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o
obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o
obj-$(CONFIG_PERF_EVENTS) += perf_event.o obj-$(CONFIG_RISCV_BASE_PMU) += perf_event.o
obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o
obj-$(CONFIG_RISCV_SBI) += sbi.o obj-$(CONFIG_RISCV_SBI) += sbi.o
......
...@@ -147,7 +147,7 @@ static int riscv_map_hw_event(u64 config) ...@@ -147,7 +147,7 @@ static int riscv_map_hw_event(u64 config)
return riscv_pmu->hw_events[config]; return riscv_pmu->hw_events[config];
} }
int riscv_map_cache_decode(u64 config, unsigned int *type, static int riscv_map_cache_decode(u64 config, unsigned int *type,
unsigned int *op, unsigned int *result) unsigned int *op, unsigned int *result)
{ {
return -ENOENT; return -ENOENT;
...@@ -342,7 +342,7 @@ static void riscv_pmu_del(struct perf_event *event, int flags) ...@@ -342,7 +342,7 @@ static void riscv_pmu_del(struct perf_event *event, int flags)
static DEFINE_MUTEX(pmc_reserve_mutex); static DEFINE_MUTEX(pmc_reserve_mutex);
irqreturn_t riscv_base_pmu_handle_irq(int irq_num, void *dev) static irqreturn_t riscv_base_pmu_handle_irq(int irq_num, void *dev)
{ {
return IRQ_NONE; return IRQ_NONE;
} }
...@@ -361,7 +361,7 @@ static int reserve_pmc_hardware(void) ...@@ -361,7 +361,7 @@ static int reserve_pmc_hardware(void)
return err; return err;
} }
void release_pmc_hardware(void) static void release_pmc_hardware(void)
{ {
mutex_lock(&pmc_reserve_mutex); mutex_lock(&pmc_reserve_mutex);
if (riscv_pmu->irq >= 0) if (riscv_pmu->irq >= 0)
...@@ -464,7 +464,7 @@ static const struct of_device_id riscv_pmu_of_ids[] = { ...@@ -464,7 +464,7 @@ static const struct of_device_id riscv_pmu_of_ids[] = {
{ /* sentinel value */ } { /* sentinel value */ }
}; };
int __init init_hw_perf_events(void) static int __init init_hw_perf_events(void)
{ {
struct device_node *node = of_find_node_by_type(NULL, "pmu"); struct device_node *node = of_find_node_by_type(NULL, "pmu");
const struct of_device_id *of_id; const struct of_device_id *of_id;
......
...@@ -65,7 +65,7 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs, ...@@ -65,7 +65,7 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
#else /* !CONFIG_FRAME_POINTER */ #else /* !CONFIG_FRAME_POINTER */
static void notrace walk_stackframe(struct task_struct *task, void notrace walk_stackframe(struct task_struct *task,
struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg) struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg)
{ {
unsigned long sp, pc; unsigned long sp, pc;
......
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