Commit 6861a197 authored by Jonghwan Choi's avatar Jonghwan Choi Committed by Kukjin Kim

ARM: EXYNOS4: Fix wrong pll type for vpll

The PLL4650C is used for VPLL on EXYNOS4 so should be fixed.
Signed-off-by: default avatarJonghwan Choi <jhbird.choi@samsung.com>
[kgene.kim@samsung.com: added message]
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent b6fd41e2
...@@ -1160,7 +1160,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) ...@@ -1160,7 +1160,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
__raw_readl(S5P_VPLL_CON1), pll_4650); __raw_readl(S5P_VPLL_CON1), pll_4650c);
clk_fout_apll.ops = &exynos4_fout_apll_ops; clk_fout_apll.ops = &exynos4_fout_apll_ops;
clk_fout_mpll.rate = mpll; clk_fout_mpll.rate = mpll;
......
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