Commit 68ed78b5 authored by Ivan Mikhaylov's avatar Ivan Mikhaylov Committed by Jakub Kicinski

net: ftgmac100: move phy connect out from ftgmac100_setup_mdio

Split MDIO registration and PHY connect into ftgmac100_setup_mdio and
ftgmac100_mii_probe.
Signed-off-by: default avatarIvan Mikhaylov <i.mikhaylov@yadro.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 338b5da3
......@@ -1044,10 +1044,39 @@ static void ftgmac100_adjust_link(struct net_device *netdev)
schedule_work(&priv->reset_task);
}
static int ftgmac100_mii_probe(struct ftgmac100 *priv, phy_interface_t intf)
static int ftgmac100_mii_probe(struct net_device *netdev)
{
struct net_device *netdev = priv->netdev;
struct ftgmac100 *priv = netdev_priv(netdev);
struct platform_device *pdev = to_platform_device(priv->dev);
struct device_node *np = pdev->dev.of_node;
struct phy_device *phydev;
phy_interface_t phy_intf;
int err;
/* Default to RGMII. It's a gigabit part after all */
err = of_get_phy_mode(np, &phy_intf);
if (err)
phy_intf = PHY_INTERFACE_MODE_RGMII;
/* Aspeed only supports these. I don't know about other IP
* block vendors so I'm going to just let them through for
* now. Note that this is only a warning if for some obscure
* reason the DT really means to lie about it or it's a newer
* part we don't know about.
*
* On the Aspeed SoC there are additionally straps and SCU
* control bits that could tell us what the interface is
* (or allow us to configure it while the IP block is held
* in reset). For now I chose to keep this driver away from
* those SoC specific bits and assume the device-tree is
* right and the SCU has been configured properly by pinmux
* or the firmware.
*/
if (priv->is_aspeed && !(phy_interface_mode_is_rgmii(phy_intf))) {
netdev_warn(netdev,
"Unsupported PHY mode %s !\n",
phy_modes(phy_intf));
}
phydev = phy_find_first(priv->mii_bus);
if (!phydev) {
......@@ -1056,7 +1085,7 @@ static int ftgmac100_mii_probe(struct ftgmac100 *priv, phy_interface_t intf)
}
phydev = phy_connect(netdev, phydev_name(phydev),
&ftgmac100_adjust_link, intf);
&ftgmac100_adjust_link, phy_intf);
if (IS_ERR(phydev)) {
netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
......@@ -1601,7 +1630,6 @@ static int ftgmac100_setup_mdio(struct net_device *netdev)
{
struct ftgmac100 *priv = netdev_priv(netdev);
struct platform_device *pdev = to_platform_device(priv->dev);
phy_interface_t phy_intf = PHY_INTERFACE_MODE_RGMII;
struct device_node *np = pdev->dev.of_node;
int i, err = 0;
u32 reg;
......@@ -1623,39 +1651,6 @@ static int ftgmac100_setup_mdio(struct net_device *netdev)
iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
}
/* Get PHY mode from device-tree */
if (np) {
/* Default to RGMII. It's a gigabit part after all */
err = of_get_phy_mode(np, &phy_intf);
if (err)
phy_intf = PHY_INTERFACE_MODE_RGMII;
/* Aspeed only supports these. I don't know about other IP
* block vendors so I'm going to just let them through for
* now. Note that this is only a warning if for some obscure
* reason the DT really means to lie about it or it's a newer
* part we don't know about.
*
* On the Aspeed SoC there are additionally straps and SCU
* control bits that could tell us what the interface is
* (or allow us to configure it while the IP block is held
* in reset). For now I chose to keep this driver away from
* those SoC specific bits and assume the device-tree is
* right and the SCU has been configured properly by pinmux
* or the firmware.
*/
if (priv->is_aspeed &&
phy_intf != PHY_INTERFACE_MODE_RMII &&
phy_intf != PHY_INTERFACE_MODE_RGMII &&
phy_intf != PHY_INTERFACE_MODE_RGMII_ID &&
phy_intf != PHY_INTERFACE_MODE_RGMII_RXID &&
phy_intf != PHY_INTERFACE_MODE_RGMII_TXID) {
netdev_warn(netdev,
"Unsupported PHY mode %s !\n",
phy_modes(phy_intf));
}
}
priv->mii_bus->name = "ftgmac100_mdio";
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
pdev->name, pdev->id);
......@@ -1673,29 +1668,28 @@ static int ftgmac100_setup_mdio(struct net_device *netdev)
goto err_register_mdiobus;
}
err = ftgmac100_mii_probe(priv, phy_intf);
if (err) {
dev_err(priv->dev, "MII Probe failed!\n");
goto err_mii_probe;
}
return 0;
err_mii_probe:
mdiobus_unregister(priv->mii_bus);
err_register_mdiobus:
mdiobus_free(priv->mii_bus);
return err;
}
static void ftgmac100_phy_disconnect(struct net_device *netdev)
{
if (!netdev->phydev)
return;
phy_disconnect(netdev->phydev);
}
static void ftgmac100_destroy_mdio(struct net_device *netdev)
{
struct ftgmac100 *priv = netdev_priv(netdev);
if (!netdev->phydev)
if (!priv->mii_bus)
return;
phy_disconnect(netdev->phydev);
mdiobus_unregister(priv->mii_bus);
mdiobus_free(priv->mii_bus);
}
......@@ -1830,14 +1824,14 @@ static int ftgmac100_probe(struct platform_device *pdev)
if (np && of_get_property(np, "use-ncsi", NULL)) {
if (!IS_ENABLED(CONFIG_NET_NCSI)) {
dev_err(&pdev->dev, "NCSI stack not enabled\n");
goto err_ncsi_dev;
goto err_phy_connect;
}
dev_info(&pdev->dev, "Using NCSI interface\n");
priv->use_ncsi = true;
priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
if (!priv->ndev)
goto err_ncsi_dev;
goto err_phy_connect;
} else if (np && of_get_property(np, "phy-handle", NULL)) {
struct phy_device *phy;
......@@ -1865,12 +1859,19 @@ static int ftgmac100_probe(struct platform_device *pdev)
err = ftgmac100_setup_mdio(netdev);
if (err)
goto err_setup_mdio;
err = ftgmac100_mii_probe(netdev);
if (err) {
dev_err(priv->dev, "MII probe failed!\n");
goto err_ncsi_dev;
}
}
if (priv->is_aspeed) {
err = ftgmac100_setup_clk(priv);
if (err)
goto err_ncsi_dev;
goto err_phy_connect;
}
/* Default ring sizes */
......@@ -1906,6 +1907,8 @@ static int ftgmac100_probe(struct platform_device *pdev)
err_register_netdev:
clk_disable_unprepare(priv->rclk);
clk_disable_unprepare(priv->clk);
err_phy_connect:
ftgmac100_phy_disconnect(netdev);
err_ncsi_dev:
ftgmac100_destroy_mdio(netdev);
err_setup_mdio:
......@@ -1936,6 +1939,7 @@ static int ftgmac100_remove(struct platform_device *pdev)
*/
cancel_work_sync(&priv->reset_task);
ftgmac100_phy_disconnect(netdev);
ftgmac100_destroy_mdio(netdev);
iounmap(priv->base);
......
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