Commit 69138480 authored by James Zhu's avatar James Zhu Committed by Alex Deucher

drm/amdgpu: use VCN firmware offset for cache window

Since we are using the signed FW now, and also using PSP firmware loading,
but it's still potential to break driver when loading FW directly
instead of PSP, so we should add offset.
Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 668a9469
...@@ -396,11 +396,8 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev) ...@@ -396,11 +396,8 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
upper_32_bits(adev->vcn.inst[i].gpu_addr)); upper_32_bits(adev->vcn.inst[i].gpu_addr));
offset = size; offset = size;
/* No signed header for now from firmware
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
AMDGPU_UVD_FIRMWARE_OFFSET >> 3); AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
*/
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
} }
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
......
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