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Commit 69205931 authored by Ramalingam C's avatar Ramalingam C Committed by Uma Shankar
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drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+ 

>From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.

Hence required changes in HW programming is handled here.

As ME FW needs the transcoder detail on which HDCP is enabled
on Gen12+ platform, we are populating the detail in hdcp_port_data.

v2:
  _MMIO_TRANS is used [Lucas and Daniel]
  platform check is moved into the caller [Lucas]
v3:
  platform check is moved into a macro [Shashank]
v4:
  Few optimizations in the coding [Shashank]
v5:
  Fixed alignment in macro definition in i915_reg.h [Shashank]
  unused variables "reg" is removed.
v6:
  Configuring the transcoder at compute_config.
  transcoder is used instead of pipe in macros.
  Rebased.
v7:
  transcoder is cached at intel_hdcp
  hdcp_port_data is configured with transcoder index asper ME FW.
v8:
  s/trans/cpu_transcoder
  s/tc/cpu_transcoder
v9:
  rep_ctl is prepared for TCD too.
  return moved into deault of rep_ctl prepare function [Shashank]
Signed-off-by: default avatarRamalingam C <ramalingam.c@intel.com>
Reviewed-by: default avatarShashank Sharma <shashank.sharma@intel.com>
Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190828164216.405-7-ramalingam.c@intel.com
parent 39e2df09
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Showing with 221 additions and 65 deletions
drivers/gpu/drm/i915/display/intel_hdcp.c
View file @ 69205931
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drivers/gpu/drm/i915/display/intel_hdmi.c
View file @ 69205931
......@@ -1491,7 +1491,10 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
{
struct drm_i915_private *dev_priv =
intel_dig_port->base.base.dev->dev_private;
struct intel_connector *connector =
intel_dig_port->hdmi.attached_connector;
enum port port = intel_dig_port->base.port;
enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
int ret;
union {
u32 reg;
......@@ -1502,13 +1505,14 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
if (ret)
return false;
I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
/* Wait for Ri prime match */
if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
I915_READ(PORT_HDCP_STATUS(port)));
I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
port)));
return false;
}
return true;
......
drivers/gpu/drm/i915/i915_reg.h
View file @ 69205931
......@@ -9281,12 +9281,20 @@ enum skl_power_gate {
/* HDCP Repeater Registers */
#define HDCP_REP_CTL _MMIO(0x66d00)
#define HDCP_TRANSA_REP_PRESENT BIT(31)
#define HDCP_TRANSB_REP_PRESENT BIT(30)
#define HDCP_TRANSC_REP_PRESENT BIT(29)
#define HDCP_TRANSD_REP_PRESENT BIT(28)
#define HDCP_DDIB_REP_PRESENT BIT(30)
#define HDCP_DDIA_REP_PRESENT BIT(29)
#define HDCP_DDIC_REP_PRESENT BIT(28)
#define HDCP_DDID_REP_PRESENT BIT(27)
#define HDCP_DDIF_REP_PRESENT BIT(26)
#define HDCP_DDIE_REP_PRESENT BIT(25)
#define HDCP_TRANSA_SHA1_M0 (1 << 20)
#define HDCP_TRANSB_SHA1_M0 (2 << 20)
#define HDCP_TRANSC_SHA1_M0 (3 << 20)
#define HDCP_TRANSD_SHA1_M0 (4 << 20)
#define HDCP_DDIB_SHA1_M0 (1 << 20)
#define HDCP_DDIA_SHA1_M0 (2 << 20)
#define HDCP_DDIC_SHA1_M0 (3 << 20)
......@@ -9326,15 +9334,92 @@ enum skl_power_gate {
_PORTE_HDCP_AUTHENC, \
_PORTF_HDCP_AUTHENC) + (x))
#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
#define _TRANSA_HDCP_CONF 0x66400
#define _TRANSB_HDCP_CONF 0x66500
#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
_TRANSB_HDCP_CONF)
#define HDCP_CONF(dev_priv, trans, port) \
(INTEL_GEN(dev_priv) >= 12 ? \
TRANS_HDCP_CONF(trans) : \
PORT_HDCP_CONF(port))
#define HDCP_CONF_CAPTURE_AN BIT(0)
#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
#define _TRANSA_HDCP_ANINIT 0x66404
#define _TRANSB_HDCP_ANINIT 0x66504
#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \
_TRANSA_HDCP_ANINIT, \
_TRANSB_HDCP_ANINIT)
#define HDCP_ANINIT(dev_priv, trans, port) \
(INTEL_GEN(dev_priv) >= 12 ? \
TRANS_HDCP_ANINIT(trans) : \
PORT_HDCP_ANINIT(port))
#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
#define _TRANSA_HDCP_ANLO 0x66408
#define _TRANSB_HDCP_ANLO 0x66508
#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
_TRANSB_HDCP_ANLO)
#define HDCP_ANLO(dev_priv, trans, port) \
(INTEL_GEN(dev_priv) >= 12 ? \
TRANS_HDCP_ANLO(trans) : \
PORT_HDCP_ANLO(port))
#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
#define _TRANSA_HDCP_ANHI 0x6640C
#define _TRANSB_HDCP_ANHI 0x6650C
#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
_TRANSB_HDCP_ANHI)
#define HDCP_ANHI(dev_priv, trans, port) \
(INTEL_GEN(dev_priv) >= 12 ? \
TRANS_HDCP_ANHI(trans) : \
PORT_HDCP_ANHI(port))
#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
#define _TRANSA_HDCP_BKSVLO 0x66410
#define _TRANSB_HDCP_BKSVLO 0x66510
#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \
_TRANSA_HDCP_BKSVLO, \
_TRANSB_HDCP_BKSVLO)
#define HDCP_BKSVLO(dev_priv, trans, port) \
(INTEL_GEN(dev_priv) >= 12 ? \
TRANS_HDCP_BKSVLO(trans) : \
PORT_HDCP_BKSVLO(port))
#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
#define _TRANSA_HDCP_BKSVHI 0x66414
#define _TRANSB_HDCP_BKSVHI 0x66514
#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \
_TRANSA_HDCP_BKSVHI, \
_TRANSB_HDCP_BKSVHI)
#define HDCP_BKSVHI(dev_priv, trans, port) \
(INTEL_GEN(dev_priv) >= 12 ? \
TRANS_HDCP_BKSVHI(trans) : \
PORT_HDCP_BKSVHI(port))
#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
#define _TRANSA_HDCP_RPRIME 0x66418
#define _TRANSB_HDCP_RPRIME 0x66518
#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \
_TRANSA_HDCP_RPRIME, \
_TRANSB_HDCP_RPRIME)
#define HDCP_RPRIME(dev_priv, trans, port) \
(INTEL_GEN(dev_priv) >= 12 ? \
TRANS_HDCP_RPRIME(trans) : \
PORT_HDCP_RPRIME(port))
#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
#define _TRANSA_HDCP_STATUS 0x6641C
#define _TRANSB_HDCP_STATUS 0x6651C
#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \
_TRANSA_HDCP_STATUS, \
_TRANSB_HDCP_STATUS)
#define HDCP_STATUS(dev_priv, trans, port) \
(INTEL_GEN(dev_priv) >= 12 ? \
TRANS_HDCP_STATUS(trans) : \
PORT_HDCP_STATUS(port))
#define HDCP_STATUS_STREAM_A_ENC BIT(31)
#define HDCP_STATUS_STREAM_B_ENC BIT(30)
#define HDCP_STATUS_STREAM_C_ENC BIT(29)
......@@ -9361,23 +9446,44 @@ enum skl_power_gate {
_PORTD_HDCP2_BASE, \
_PORTE_HDCP2_BASE, \
_PORTF_HDCP2_BASE) + (x))
#define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port, 0x98)
#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
#define _TRANSA_HDCP2_AUTH 0x66498
#define _TRANSB_HDCP2_AUTH 0x66598
#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
_TRANSB_HDCP2_AUTH)
#define AUTH_LINK_AUTHENTICATED BIT(31)
#define AUTH_LINK_TYPE BIT(30)
#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
#define AUTH_CLR_KEYS BIT(18)
#define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0)
#define HDCP2_AUTH(dev_priv, trans, port) \
(INTEL_GEN(dev_priv) >= 12 ? \
TRANS_HDCP2_AUTH(trans) : \
PORT_HDCP2_AUTH(port))
#define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0)
#define _TRANSA_HDCP2_CTL 0x664B0
#define _TRANSB_HDCP2_CTL 0x665B0
#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
_TRANSB_HDCP2_CTL)
#define CTL_LINK_ENCRYPTION_REQ BIT(31)
#define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4)
#define STREAM_ENCRYPTION_STATUS_A BIT(31)
#define STREAM_ENCRYPTION_STATUS_B BIT(30)
#define STREAM_ENCRYPTION_STATUS_C BIT(29)
#define HDCP2_CTL(dev_priv, trans, port) \
(INTEL_GEN(dev_priv) >= 12 ? \
TRANS_HDCP2_CTL(trans) : \
PORT_HDCP2_CTL(port))
#define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4)
#define _TRANSA_HDCP2_STATUS 0x664B4
#define _TRANSB_HDCP2_STATUS 0x665B4
#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \
_TRANSA_HDCP2_STATUS, \
_TRANSB_HDCP2_STATUS)
#define LINK_TYPE_STATUS BIT(22)
#define LINK_AUTH_STATUS BIT(21)
#define LINK_ENCRYPTION_STATUS BIT(20)
#define HDCP2_STATUS(dev_priv, trans, port) \
(INTEL_GEN(dev_priv) >= 12 ? \
TRANS_HDCP2_STATUS(trans) : \
PORT_HDCP2_STATUS(port))
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
......
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