Commit 6982dba1 authored by Heiko Carstens's avatar Heiko Carstens Committed by Vasily Gorbik

s390/alternatives: use insn format for new instructions

Use insn format with instruction format specifier instead of plain
longs. This way it is also more obvious that code instead of data is
generated.

The generated code is identical.
Signed-off-by: default avatarHeiko Carstens <hca@linux.ibm.com>
Signed-off-by: default avatarVasily Gorbik <gor@linux.ibm.com>
parent 4afeb670
...@@ -78,7 +78,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *lp) ...@@ -78,7 +78,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *lp)
{ {
typecheck(int, lp->lock); typecheck(int, lp->lock);
asm_inline volatile( asm_inline volatile(
ALTERNATIVE("", ".long 0xb2fa0070", 49) /* NIAI 7 */ ALTERNATIVE("", ".insn rre,0xb2fa0000,7,0", 49) /* NIAI 7 */
" sth %1,%0\n" " sth %1,%0\n"
: "=R" (((unsigned short *) &lp->lock)[1]) : "=R" (((unsigned short *) &lp->lock)[1])
: "d" (0) : "cc", "memory"); : "d" (0) : "cc", "memory");
......
...@@ -121,22 +121,22 @@ _LPP_OFFSET = __LC_LPP ...@@ -121,22 +121,22 @@ _LPP_OFFSET = __LC_LPP
.endm .endm
.macro BPOFF .macro BPOFF
ALTERNATIVE "", ".long 0xb2e8c000", 82 ALTERNATIVE "", ".insn rrf,0xb2e80000,0,0,12,0", 82
.endm .endm
.macro BPON .macro BPON
ALTERNATIVE "", ".long 0xb2e8d000", 82 ALTERNATIVE "", ".insn rrf,0xb2e80000,0,0,13,0", 82
.endm .endm
.macro BPENTER tif_ptr,tif_mask .macro BPENTER tif_ptr,tif_mask
ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .long 0xb2e8d000", \ ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .insn rrf,0xb2e80000,0,0,13,0", \
"", 82 "", 82
.endm .endm
.macro BPEXIT tif_ptr,tif_mask .macro BPEXIT tif_ptr,tif_mask
TSTMSK \tif_ptr,\tif_mask TSTMSK \tif_ptr,\tif_mask
ALTERNATIVE "jz .+8; .long 0xb2e8c000", \ ALTERNATIVE "jz .+8; .insn rrf,0xb2e80000,0,0,12,0", \
"jnz .+8; .long 0xb2e8d000", 82 "jnz .+8; .insn rrf,0xb2e80000,0,0,13,0", 82
.endm .endm
/* /*
......
...@@ -75,7 +75,7 @@ static inline int arch_load_niai4(int *lock) ...@@ -75,7 +75,7 @@ static inline int arch_load_niai4(int *lock)
int owner; int owner;
asm_inline volatile( asm_inline volatile(
ALTERNATIVE("", ".long 0xb2fa0040", 49) /* NIAI 4 */ ALTERNATIVE("", ".insn rre,0xb2fa0000,4,0", 49) /* NIAI 4 */
" l %0,%1\n" " l %0,%1\n"
: "=d" (owner) : "Q" (*lock) : "memory"); : "=d" (owner) : "Q" (*lock) : "memory");
return owner; return owner;
...@@ -86,7 +86,7 @@ static inline int arch_cmpxchg_niai8(int *lock, int old, int new) ...@@ -86,7 +86,7 @@ static inline int arch_cmpxchg_niai8(int *lock, int old, int new)
int expected = old; int expected = old;
asm_inline volatile( asm_inline volatile(
ALTERNATIVE("", ".long 0xb2fa0080", 49) /* NIAI 8 */ ALTERNATIVE("", ".insn rre,0xb2fa0000,8,0", 49) /* NIAI 8 */
" cs %0,%3,%1\n" " cs %0,%3,%1\n"
: "=d" (old), "=Q" (*lock) : "=d" (old), "=Q" (*lock)
: "0" (old), "d" (new), "Q" (*lock) : "0" (old), "d" (new), "Q" (*lock)
......
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