Commit 699c0193 authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller

tg3: Fix 57765 EEE support

EEE support in the 57765 internal phy will not enable after a phy reset
unless it sees that EEE is supported in the MAC.  This patch moves the
code that programs the CPMU EEE registers to a place before the phy
reset.
Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Reviewed-by: default avatarBenjamin Li <benli@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3110f5f5
...@@ -7809,6 +7809,22 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) ...@@ -7809,6 +7809,22 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
tg3_abort_hw(tp, 1); tg3_abort_hw(tp, 1);
/* Enable MAC control of LPI */
if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
TG3_CPMU_EEE_LNKIDL_UART_IDL);
tw32_f(TG3_CPMU_EEE_CTRL,
TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
tw32_f(TG3_CPMU_EEE_MODE,
TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
TG3_CPMU_EEEMD_LPI_IN_TX |
TG3_CPMU_EEEMD_LPI_IN_RX |
TG3_CPMU_EEEMD_EEE_ENABLE);
}
if (reset_phy) if (reset_phy)
tg3_phy_reset(tp); tg3_phy_reset(tp);
...@@ -7890,22 +7906,6 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) ...@@ -7890,22 +7906,6 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
tw32(TG3_CPMU_LSPD_10MB_CLK, val); tw32(TG3_CPMU_LSPD_10MB_CLK, val);
} }
/* Enable MAC control of LPI */
if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
TG3_CPMU_EEE_LNKIDL_UART_IDL);
tw32_f(TG3_CPMU_EEE_CTRL,
TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
tw32_f(TG3_CPMU_EEE_MODE,
TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
TG3_CPMU_EEEMD_LPI_IN_TX |
TG3_CPMU_EEEMD_LPI_IN_RX |
TG3_CPMU_EEEMD_EEE_ENABLE);
}
/* This works around an issue with Athlon chipsets on /* This works around an issue with Athlon chipsets on
* B3 tigon3 silicon. This bit has no effect on any * B3 tigon3 silicon. This bit has no effect on any
* other revision. But do not set this on PCI Express * other revision. But do not set this on PCI Express
......
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