Commit 69bfec75 authored by Emil Renner Berthing's avatar Emil Renner Berthing Committed by Conor Dooley

reset: Create subdirectory for StarFive drivers

This moves the StarFive JH7100 reset driver to a new subdirectory in
preparation for adding more StarFive reset drivers.
Reviewed-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Tested-by: default avatarTommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: default avatarEmil Renner Berthing <kernel@esmil.dk>
Signed-off-by: default avatarHal Feng <hal.feng@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent c49a757a
...@@ -232,13 +232,6 @@ config RESET_SOCFPGA ...@@ -232,13 +232,6 @@ config RESET_SOCFPGA
This enables the reset driver for the SoCFPGA ARMv7 platforms. This This enables the reset driver for the SoCFPGA ARMv7 platforms. This
driver gets initialized early during platform init calls. driver gets initialized early during platform init calls.
config RESET_STARFIVE_JH7100
bool "StarFive JH7100 Reset Driver"
depends on ARCH_STARFIVE || COMPILE_TEST
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JH7100 SoC.
config RESET_SUNPLUS config RESET_SUNPLUS
bool "Sunplus SoCs Reset Driver" if COMPILE_TEST bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
default ARCH_SUNPLUS default ARCH_SUNPLUS
...@@ -320,6 +313,7 @@ config RESET_ZYNQ ...@@ -320,6 +313,7 @@ config RESET_ZYNQ
help help
This enables the reset controller driver for Xilinx Zynq SoCs. This enables the reset controller driver for Xilinx Zynq SoCs.
source "drivers/reset/starfive/Kconfig"
source "drivers/reset/sti/Kconfig" source "drivers/reset/sti/Kconfig"
source "drivers/reset/hisilicon/Kconfig" source "drivers/reset/hisilicon/Kconfig"
source "drivers/reset/tegra/Kconfig" source "drivers/reset/tegra/Kconfig"
......
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
obj-y += core.o obj-y += core.o
obj-y += hisilicon/ obj-y += hisilicon/
obj-y += starfive/
obj-$(CONFIG_ARCH_STI) += sti/ obj-$(CONFIG_ARCH_STI) += sti/
obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
...@@ -30,7 +31,6 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o ...@@ -30,7 +31,6 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
......
# SPDX-License-Identifier: GPL-2.0-only
config RESET_STARFIVE_JH7100
bool "StarFive JH7100 Reset Driver"
depends on ARCH_STARFIVE || COMPILE_TEST
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JH7100 SoC.
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
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