Commit 6a588703 authored by James Liao's avatar James Liao Committed by Stephen Boyd

dt-bindings: ARM: Mediatek: Document bindings for MT2701

This patch adds the binding documentation for apmixedsys, bdpsys,
ethsys, hifsys, imgsys, infracfg, mmsys, pericfg, topckgen and
vdecsys for Mediatek MT2701.
Signed-off-by: default avatarJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: default avatarErin Lo <erin.lo@mediatek.com>
Tested-by: default avatarJohn Crispin <blogic@openwrt.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 2886c846
...@@ -5,7 +5,8 @@ The Mediatek apmixedsys controller provides the PLLs to the system. ...@@ -5,7 +5,8 @@ The Mediatek apmixedsys controller provides the PLLs to the system.
Required Properties: Required Properties:
- compatible: Should be: - compatible: Should be one of:
- "mediatek,mt2701-apmixedsys"
- "mediatek,mt8135-apmixedsys" - "mediatek,mt8135-apmixedsys"
- "mediatek,mt8173-apmixedsys" - "mediatek,mt8173-apmixedsys"
- #clock-cells: Must be 1 - #clock-cells: Must be 1
......
Mediatek bdpsys controller
============================
The Mediatek bdpsys controller provides various clocks to the system.
Required Properties:
- compatible: Should be:
- "mediatek,mt2701-bdpsys", "syscon"
- #clock-cells: Must be 1
The bdpsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
bdpsys: clock-controller@1c000000 {
compatible = "mediatek,mt2701-bdpsys", "syscon";
reg = <0 0x1c000000 0 0x1000>;
#clock-cells = <1>;
};
Mediatek ethsys controller
============================
The Mediatek ethsys controller provides various clocks to the system.
Required Properties:
- compatible: Should be:
- "mediatek,mt2701-ethsys", "syscon"
- #clock-cells: Must be 1
The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
ethsys: clock-controller@1b000000 {
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
};
Mediatek hifsys controller
============================
The Mediatek hifsys controller provides various clocks and reset
outputs to the system.
Required Properties:
- compatible: Should be:
- "mediatek,mt2701-hifsys", "syscon"
- #clock-cells: Must be 1
The hifsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
hifsys: clock-controller@1a000000 {
compatible = "mediatek,mt2701-hifsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...@@ -5,7 +5,8 @@ The Mediatek imgsys controller provides various clocks to the system. ...@@ -5,7 +5,8 @@ The Mediatek imgsys controller provides various clocks to the system.
Required Properties: Required Properties:
- compatible: Should be: - compatible: Should be one of:
- "mediatek,mt2701-imgsys", "syscon"
- "mediatek,mt8173-imgsys", "syscon" - "mediatek,mt8173-imgsys", "syscon"
- #clock-cells: Must be 1 - #clock-cells: Must be 1
......
...@@ -6,7 +6,8 @@ outputs to the system. ...@@ -6,7 +6,8 @@ outputs to the system.
Required Properties: Required Properties:
- compatible: Should be: - compatible: Should be one of:
- "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon"
- #clock-cells: Must be 1 - #clock-cells: Must be 1
......
...@@ -5,7 +5,8 @@ The Mediatek mmsys controller provides various clocks to the system. ...@@ -5,7 +5,8 @@ The Mediatek mmsys controller provides various clocks to the system.
Required Properties: Required Properties:
- compatible: Should be: - compatible: Should be one of:
- "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon" - "mediatek,mt8173-mmsys", "syscon"
- #clock-cells: Must be 1 - #clock-cells: Must be 1
......
...@@ -6,7 +6,8 @@ outputs to the system. ...@@ -6,7 +6,8 @@ outputs to the system.
Required Properties: Required Properties:
- compatible: Should be: - compatible: Should be one of:
- "mediatek,mt2701-pericfg", "syscon"
- "mediatek,mt8135-pericfg", "syscon" - "mediatek,mt8135-pericfg", "syscon"
- "mediatek,mt8173-pericfg", "syscon" - "mediatek,mt8173-pericfg", "syscon"
- #clock-cells: Must be 1 - #clock-cells: Must be 1
......
...@@ -5,7 +5,8 @@ The Mediatek topckgen controller provides various clocks to the system. ...@@ -5,7 +5,8 @@ The Mediatek topckgen controller provides various clocks to the system.
Required Properties: Required Properties:
- compatible: Should be: - compatible: Should be one of:
- "mediatek,mt2701-topckgen"
- "mediatek,mt8135-topckgen" - "mediatek,mt8135-topckgen"
- "mediatek,mt8173-topckgen" - "mediatek,mt8173-topckgen"
- #clock-cells: Must be 1 - #clock-cells: Must be 1
......
...@@ -5,7 +5,8 @@ The Mediatek vdecsys controller provides various clocks to the system. ...@@ -5,7 +5,8 @@ The Mediatek vdecsys controller provides various clocks to the system.
Required Properties: Required Properties:
- compatible: Should be: - compatible: Should be one of:
- "mediatek,mt2701-vdecsys", "syscon"
- "mediatek,mt8173-vdecsys", "syscon" - "mediatek,mt8173-vdecsys", "syscon"
- #clock-cells: Must be 1 - #clock-cells: Must be 1
......
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