Commit 6ab6b4ec authored by Eugen Hristev's avatar Eugen Hristev Committed by Jonathan Cameron

Documentation: dt: iio: at91-sama5d2_adc: add hw trigger edge binding

Add property for the edge type of the hardware trigger pin ADTRG
Signed-off-by: default avatarEugen Hristev <eugen.hristev@microchip.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarLudovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: default avatarJonathan Cameron <jic23@kernel.org>
parent edd80a5f
...@@ -11,6 +11,11 @@ Required properties: ...@@ -11,6 +11,11 @@ Required properties:
- atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC. - atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC.
- atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC. - atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC.
- atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC. - atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC.
- atmel,trigger-edge-type: One of possible edge types for the ADTRG hardware
trigger pin. When the specific edge type is detected, the conversion will
start. Possible values are rising, falling, or both.
This property uses the IRQ edge types values: IRQ_TYPE_EDGE_RISING ,
IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH
Example: Example:
...@@ -25,4 +30,5 @@ adc: adc@fc030000 { ...@@ -25,4 +30,5 @@ adc: adc@fc030000 {
atmel,startup-time-ms = <4>; atmel,startup-time-ms = <4>;
vddana-supply = <&vdd_3v3_lp_reg>; vddana-supply = <&vdd_3v3_lp_reg>;
vref-supply = <&vdd_3v3_lp_reg>; vref-supply = <&vdd_3v3_lp_reg>;
atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
} }
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