Commit 6aed4684 authored by Bjorn Helgaas's avatar Bjorn Helgaas

Merge branch 'pci/host-tango' into next

* pci/host-tango:
  PCI: tango: Add Sigma Designs Tango SMP8759 PCIe host bridge support
  PCI: Add DT binding for Sigma Designs Tango PCIe controller

Conflicts:
	drivers/pci/host/Kconfig
	drivers/pci/host/Makefile
parents 7542a046 5e14e9fa
Sigma Designs Tango PCIe controller
Required properties:
- compatible: "sigma,smp8759-pcie"
- reg: address/size of PCI configuration space, address/size of register area
- bus-range: defined by size of PCI configuration space
- device_type: "pci"
- #size-cells: <2>
- #address-cells: <3>
- msi-controller
- ranges: translation from system to bus addresses
- interrupts: spec for misc interrupts, spec for MSI
Example:
pcie@2e000 {
compatible = "sigma,smp8759-pcie";
reg = <0x50000000 0x400000>, <0x2e000 0x100>;
bus-range = <0 3>;
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
msi-controller;
ranges = <0x02000000 0x0 0x00400000 0x50400000 0x0 0x3c00000>;
interrupts =
<54 IRQ_TYPE_LEVEL_HIGH>, /* misc interrupts */
<55 IRQ_TYPE_LEVEL_HIGH>; /* MSI */
};
......@@ -191,6 +191,20 @@ config PCIE_MEDIATEK
MT7623 series SoCs. There is one single root complex with 3 root
ports available. Each port supports Gen2 lane x1.
config PCIE_TANGO_SMP8759
bool "Tango SMP8759 PCIe controller (DANGEROUS)"
depends on ARCH_TANGO && PCI_MSI && OF
depends on BROKEN
select PCI_HOST_COMMON
help
Say Y here to enable PCIe controller support for Sigma Designs
Tango SMP8759-based systems.
Note: The SMP8759 controller multiplexes PCI config and MMIO
accesses, and Linux doesn't provide a way to serialize them.
This can lead to data corruption if drivers perform concurrent
config and MMIO accesses.
config VMD
depends on PCI_MSI && X86_64 && SRCU
tristate "Intel Volume Management Device Driver"
......
......@@ -19,6 +19,7 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
obj-$(CONFIG_VMD) += vmd.o
# The following drivers are for devices that use the generic ACPI
......
#include <linux/pci-ecam.h>
#include <linux/delay.h>
#include <linux/of.h>
#define SMP8759_MUX 0x48
#define SMP8759_TEST_OUT 0x74
struct tango_pcie {
void __iomem *base;
};
static int smp8759_config_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
struct pci_config_window *cfg = bus->sysdata;
struct tango_pcie *pcie = dev_get_drvdata(cfg->parent);
int ret;
/* Reads in configuration space outside devfn 0 return garbage */
if (devfn != 0)
return PCIBIOS_FUNC_NOT_SUPPORTED;
/*
* PCI config and MMIO accesses are muxed. Linux doesn't have a
* mutual exclusion mechanism for config vs. MMIO accesses, so
* concurrent accesses may cause corruption.
*/
writel_relaxed(1, pcie->base + SMP8759_MUX);
ret = pci_generic_config_read(bus, devfn, where, size, val);
writel_relaxed(0, pcie->base + SMP8759_MUX);
return ret;
}
static int smp8759_config_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
struct pci_config_window *cfg = bus->sysdata;
struct tango_pcie *pcie = dev_get_drvdata(cfg->parent);
int ret;
writel_relaxed(1, pcie->base + SMP8759_MUX);
ret = pci_generic_config_write(bus, devfn, where, size, val);
writel_relaxed(0, pcie->base + SMP8759_MUX);
return ret;
}
static struct pci_ecam_ops smp8759_ecam_ops = {
.bus_shift = 20,
.pci_ops = {
.map_bus = pci_ecam_map_bus,
.read = smp8759_config_read,
.write = smp8759_config_write,
}
};
static int tango_pcie_link_up(struct tango_pcie *pcie)
{
void __iomem *test_out = pcie->base + SMP8759_TEST_OUT;
int i;
writel_relaxed(16, test_out);
for (i = 0; i < 10; ++i) {
u32 ltssm_state = readl_relaxed(test_out) >> 8;
if ((ltssm_state & 0x1f) == 0xf) /* L0 */
return 1;
usleep_range(3000, 4000);
}
return 0;
}
static int tango_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct tango_pcie *pcie;
struct resource *res;
int ret;
dev_warn(dev, "simultaneous PCI config and MMIO accesses may cause data corruption\n");
add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
if (!pcie)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
pcie->base = devm_ioremap_resource(dev, res);
if (IS_ERR(pcie->base))
return PTR_ERR(pcie->base);
platform_set_drvdata(pdev, pcie);
if (!tango_pcie_link_up(pcie))
return -ENODEV;
return pci_host_common_probe(pdev, &smp8759_ecam_ops);
}
static const struct of_device_id tango_pcie_ids[] = {
{ .compatible = "sigma,smp8759-pcie" },
{ },
};
static struct platform_driver tango_pcie_driver = {
.probe = tango_pcie_probe,
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = tango_pcie_ids,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver(tango_pcie_driver);
/*
* The root complex advertises the wrong device class.
* Header Type 1 is for PCI-to-PCI bridges.
*/
static void tango_fixup_class(struct pci_dev *dev)
{
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIGMA, 0x0024, tango_fixup_class);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIGMA, 0x0028, tango_fixup_class);
/*
* The root complex exposes a "fake" BAR, which is used to filter
* bus-to-system accesses. Only accesses within the range defined by this
* BAR are forwarded to the host, others are ignored.
*
* By default, the DMA framework expects an identity mapping, and DRAM0 is
* mapped at 0x80000000.
*/
static void tango_fixup_bar(struct pci_dev *dev)
{
dev->non_compliant_bars = true;
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x80000000);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIGMA, 0x0024, tango_fixup_bar);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIGMA, 0x0028, tango_fixup_bar);
......@@ -1373,6 +1373,8 @@
#define PCI_DEVICE_ID_TTI_HPT374 0x0008
#define PCI_DEVICE_ID_TTI_HPT372N 0x0009 /* apparently a 372N variant? */
#define PCI_VENDOR_ID_SIGMA 0x1105
#define PCI_VENDOR_ID_VIA 0x1106
#define PCI_DEVICE_ID_VIA_8763_0 0x0198
#define PCI_DEVICE_ID_VIA_8380_0 0x0204
......
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