ARM: dts: qcom: add pseudo random number generator on the IPQ4019

This architecture has a pseudo random number generator
supported by the existing "qcom,prng" binding.

rngtest: bits received from input: 5795960032
rngtest: FIPS 140-2 successes: 289591
rngtest: FIPS 140-2 failures: 207
rngtest: FIPS 140-2(2001-10-10) Monobit: 25
rngtest: FIPS 140-2(2001-10-10) Poker: 28
rngtest: FIPS 140-2(2001-10-10) Runs: 91
rngtest: FIPS 140-2(2001-10-10) Long run: 67
rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
rngtest: input channel speed: (min=244; avg=46122; max=3906250)Kibits/s
rngtest: FIPS tests speed: (min=1.327; avg=20.966; max=26.345)Mibits/s
rngtest: Program run time: 386965827 microseconds
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi

@@ -21,6 +21,10 @@ / {
 	compatible = "qcom,ipq4019";
 
 	soc {
+		rng@22000 {
+			status = "ok";
+		};
+
 		pinctrl@1000000 {
 			serial_pins: serial_pinmux {
 				mux {

arch/arm/boot/dts/qcom-ipq4019.dtsi

@@ -134,6 +134,14 @@ gcc: clock-controller@1800000 {
 			reg = <0x1800000 0x60000>;
 		};
 
+		rng@22000 {
+			compatible = "qcom,prng";
+			reg = <0x22000 0x140>;
+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+			clock-names = "core";
+			status = "disabled";
+		};
+
 		tlmm: pinctrl@1000000 {
 			compatible = "qcom,ipq4019-pinctrl";
 			reg = <0x01000000 0x300000>;