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Commit 6c3566c5 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Fix uncore topics for knightslanding 

Remove 'uncore-other' topic classification, move to cache, io and
memory.
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230413132949.3487664-17-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 05c74de4
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tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json 0 → 100644
View file @ 6c3566c5
[
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_0",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_1",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_0",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_0",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_1",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_0",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_0",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_1",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_0",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_0",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_0",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_0",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_0",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_0",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AD_0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_1",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AD_1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_0",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AK_0",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_1",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AK_1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_0",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_0",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_1",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_0",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.BL_0",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_1",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.BL_1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.ALL",
"EventCode": "0x10",
"EventName": "UNC_M2P_INGRESS_CYCLES_NE.ALL",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_IDI",
"EventCode": "0x10",
"EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_IDI",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCB",
"EventCode": "0x10",
"EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCB",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCS",
"EventCode": "0x10",
"EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCS",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2PCIe"
}
]
tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json
View file @ 6c3566c5
[
{
"BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.HIT_CLEAN",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.HIT_DIRTY",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.MISS_CLEAN",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.MISS_DIRTY",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Number of EDC Hits or Misses. Miss I",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.MISS_INVALID",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "ECLK count",
"EventName": "UNC_E_E_CLOCKTICKS",
"PerPkg": "1",
"Unit": "EDC_ECLK"
},
{
"BriefDescription": "Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache.",
"EventCode": "0x01",
"EventName": "UNC_E_RPQ_INSERTS",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "EDC_ECLK"
},
{
"BriefDescription": "UCLK count",
"EventName": "UNC_E_U_CLOCKTICKS",
"PerPkg": "1",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache.",
"EventCode": "0x02",
"EventName": "UNC_E_WPQ_INSERTS",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "EDC_ECLK"
},
{
"BriefDescription": "CAS All",
"EventCode": "0x03",
......
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