Commit 6c5add1c authored by Jonathan Corbet's avatar Jonathan Corbet

Merge branch 'riscv-move' into docs-mw

parents de6772ee ed843ae9
...@@ -20,7 +20,7 @@ implementation. ...@@ -20,7 +20,7 @@ implementation.
openrisc/index openrisc/index
parisc/index parisc/index
powerpc/index powerpc/index
../riscv/index riscv/index
s390/index s390/index
sh/index sh/index
sparc/index sparc/index
......
...@@ -101,7 +101,7 @@ to do something different in the near future. ...@@ -101,7 +101,7 @@ to do something different in the near future.
../doc-guide/maintainer-profile ../doc-guide/maintainer-profile
../nvdimm/maintainer-entry-profile ../nvdimm/maintainer-entry-profile
../riscv/patch-acceptance ../arch/riscv/patch-acceptance
../driver-api/media/maintainer-entry-profile ../driver-api/media/maintainer-entry-profile
../driver-api/vfio-pci-device-specific-driver-acceptance ../driver-api/vfio-pci-device-specific-driver-acceptance
../nvme/feature-and-quirk-policy ../nvme/feature-and-quirk-policy
......
...@@ -71,7 +71,7 @@ lack of a better place. ...@@ -71,7 +71,7 @@ lack of a better place.
volatile-considered-harmful volatile-considered-harmful
botching-up-ioctls botching-up-ioctls
clang-format clang-format
../riscv/patch-acceptance ../arch/riscv/patch-acceptance
../core-api/unaligned-memory-access ../core-api/unaligned-memory-access
.. only:: subproject and html .. only:: subproject and html
......
.. include:: ../disclaimer-ita.rst .. include:: ../disclaimer-ita.rst
:Original: :doc:`../../../riscv/patch-acceptance` :Original: :doc:`../../../arch/riscv/patch-acceptance`
:Translator: Federico Vaga <federico.vaga@vaga.pv.it> :Translator: Federico Vaga <federico.vaga@vaga.pv.it>
arch/riscv linee guida alla manutenzione per gli sviluppatori arch/riscv linee guida alla manutenzione per gli sviluppatori
......
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
mips/index mips/index
arm64/index arm64/index
../riscv/index ../arch/riscv/index
openrisc/index openrisc/index
parisc/index parisc/index
loongarch/index loongarch/index
......
.. include:: ../disclaimer-zh_CN.rst .. include:: ../../disclaimer-zh_CN.rst
:Original: Documentation/riscv/boot-image-header.rst :Original: Documentation/arch/riscv/boot-image-header.rst
:翻译: :翻译:
......
.. SPDX-License-Identifier: GPL-2.0 .. SPDX-License-Identifier: GPL-2.0
.. include:: ../disclaimer-zh_CN.rst .. include:: ../../disclaimer-zh_CN.rst
:Original: Documentation/riscv/index.rst :Original: Documentation/arch/riscv/index.rst
:翻译: :翻译:
......
.. SPDX-License-Identifier: GPL-2.0 .. SPDX-License-Identifier: GPL-2.0
.. include:: ../disclaimer-zh_CN.rst .. include:: ../../disclaimer-zh_CN.rst
:Original: Documentation/riscv/patch-acceptance.rst :Original: Documentation/arch/riscv/patch-acceptance.rst
:翻译: :翻译:
......
.. SPDX-License-Identifier: GPL-2.0 .. SPDX-License-Identifier: GPL-2.0
.. include:: ../disclaimer-zh_CN.rst .. include:: ../../disclaimer-zh_CN.rst
:Original: Documentation/riscv/vm-layout.rst :Original: Documentation/arch/riscv/vm-layout.rst
:翻译: :翻译:
......
...@@ -89,4 +89,4 @@ ...@@ -89,4 +89,4 @@
../doc-guide/maintainer-profile ../doc-guide/maintainer-profile
../../../nvdimm/maintainer-entry-profile ../../../nvdimm/maintainer-entry-profile
../../../riscv/patch-acceptance ../../../arch/riscv/patch-acceptance
...@@ -18424,7 +18424,7 @@ L: linux-riscv@lists.infradead.org ...@@ -18424,7 +18424,7 @@ L: linux-riscv@lists.infradead.org
S: Supported S: Supported
Q: https://patchwork.kernel.org/project/linux-riscv/list/ Q: https://patchwork.kernel.org/project/linux-riscv/list/
C: irc://irc.libera.chat/riscv C: irc://irc.libera.chat/riscv
P: Documentation/riscv/patch-acceptance.rst P: Documentation/arch/riscv/patch-acceptance.rst
T: git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
F: arch/riscv/ F: arch/riscv/
N: riscv N: riscv
......
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
/* /*
* Interface for probing hardware capabilities from userspace, see * Interface for probing hardware capabilities from userspace, see
* Documentation/riscv/hwprobe.rst for more information. * Documentation/arch/riscv/hwprobe.rst for more information.
*/ */
struct riscv_hwprobe { struct riscv_hwprobe {
__s64 key; __s64 key;
......
...@@ -79,7 +79,7 @@ SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end, ...@@ -79,7 +79,7 @@ SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end,
/* /*
* The hwprobe interface, for allowing userspace to probe to see which features * The hwprobe interface, for allowing userspace to probe to see which features
* are supported by the hardware. See Documentation/riscv/hwprobe.rst for more * are supported by the hardware. See Documentation/arch/riscv/hwprobe.rst for more
* details. * details.
*/ */
static void hwprobe_arch_id(struct riscv_hwprobe *pair, static void hwprobe_arch_id(struct riscv_hwprobe *pair,
......
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