Commit 6c63ef80 authored by John David Anglin's avatar John David Anglin Committed by Helge Deller

parisc: Remove lock code to serialize TLB operations in pacache.S

TLB operations only need to be serialized on machines with the Merced
(Stretch) bus. The only machines in this category are L and N class, and
they require a 64-bit PA 2.0 kernel. On these machines, we use local TLB
purges in the tmpalias routines.
We don't need to serialize TLB purges on all other machines. Thus, the
lock/unlock code can be removed when CONFIG_PA20 is not defined.
Further, when CONFIG_PA20 is not defined, alternative patching converts
the TLB purges to local purges when PA 2.0 hardware has been detected.
Signed-off-by: default avatarJohn David Anglin <dave.anglin@bell.net>
Tested-By: default avatarSven Schnelle <svens@stackframe.org>
Signed-off-by: default avatarHelge Deller <deller@gmx.de>
parent dbdf0760
...@@ -311,39 +311,6 @@ fdsync: ...@@ -311,39 +311,6 @@ fdsync:
nop nop
ENDPROC_CFI(flush_data_cache_local) ENDPROC_CFI(flush_data_cache_local)
/* Macros to serialize TLB purge operations on SMP. */
.macro tlb_lock la,flags,tmp
#ifdef CONFIG_SMP
98:
#if __PA_LDCW_ALIGNMENT > 4
load32 pa_tlb_lock + __PA_LDCW_ALIGNMENT-1, \la
depi 0,31,__PA_LDCW_ALIGN_ORDER, \la
#else
load32 pa_tlb_lock, \la
#endif
rsm PSW_SM_I,\flags
1: LDCW 0(\la),\tmp
cmpib,<>,n 0,\tmp,3f
2: ldw 0(\la),\tmp
cmpb,<> %r0,\tmp,1b
nop
b,n 2b
3:
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
#endif
.endm
.macro tlb_unlock la,flags,tmp
#ifdef CONFIG_SMP
98: ldi 1,\tmp
sync
stw \tmp,0(\la)
mtsm \flags
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
#endif
.endm
/* Clear page using kernel mapping. */ /* Clear page using kernel mapping. */
ENTRY_CFI(clear_page_asm) ENTRY_CFI(clear_page_asm)
...@@ -601,10 +568,8 @@ ENTRY_CFI(copy_user_page_asm) ...@@ -601,10 +568,8 @@ ENTRY_CFI(copy_user_page_asm)
pdtlb,l %r0(%r28) pdtlb,l %r0(%r28)
pdtlb,l %r0(%r29) pdtlb,l %r0(%r29)
#else #else
tlb_lock %r20,%r21,%r22
0: pdtlb %r0(%r28) 0: pdtlb %r0(%r28)
1: pdtlb %r0(%r29) 1: pdtlb %r0(%r29)
tlb_unlock %r20,%r21,%r22
ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB) ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB)
#endif #endif
...@@ -743,9 +708,7 @@ ENTRY_CFI(clear_user_page_asm) ...@@ -743,9 +708,7 @@ ENTRY_CFI(clear_user_page_asm)
#ifdef CONFIG_PA20 #ifdef CONFIG_PA20
pdtlb,l %r0(%r28) pdtlb,l %r0(%r28)
#else #else
tlb_lock %r20,%r21,%r22
0: pdtlb %r0(%r28) 0: pdtlb %r0(%r28)
tlb_unlock %r20,%r21,%r22
ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
#endif #endif
...@@ -821,9 +784,7 @@ ENTRY_CFI(flush_dcache_page_asm) ...@@ -821,9 +784,7 @@ ENTRY_CFI(flush_dcache_page_asm)
#ifdef CONFIG_PA20 #ifdef CONFIG_PA20
pdtlb,l %r0(%r28) pdtlb,l %r0(%r28)
#else #else
tlb_lock %r20,%r21,%r22
0: pdtlb %r0(%r28) 0: pdtlb %r0(%r28)
tlb_unlock %r20,%r21,%r22
ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
#endif #endif
...@@ -882,9 +843,7 @@ ENTRY_CFI(purge_dcache_page_asm) ...@@ -882,9 +843,7 @@ ENTRY_CFI(purge_dcache_page_asm)
#ifdef CONFIG_PA20 #ifdef CONFIG_PA20
pdtlb,l %r0(%r28) pdtlb,l %r0(%r28)
#else #else
tlb_lock %r20,%r21,%r22
0: pdtlb %r0(%r28) 0: pdtlb %r0(%r28)
tlb_unlock %r20,%r21,%r22
ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
#endif #endif
...@@ -948,10 +907,8 @@ ENTRY_CFI(flush_icache_page_asm) ...@@ -948,10 +907,8 @@ ENTRY_CFI(flush_icache_page_asm)
1: pitlb,l %r0(%sr4,%r28) 1: pitlb,l %r0(%sr4,%r28)
ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP) ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
#else #else
tlb_lock %r20,%r21,%r22
0: pdtlb %r0(%r28) 0: pdtlb %r0(%r28)
1: pitlb %r0(%sr4,%r28) 1: pitlb %r0(%sr4,%r28)
tlb_unlock %r20,%r21,%r22
ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB) ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB)
ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP) ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
......
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