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Commit 6e1d521b authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge branches 'depends/irqdomain' and 'at91/base2+cleanup' into next/dt 

These two branches are a dependency for the at91 device tree changes,
so we pull them in here. at91/base2+cleanup will get merged through
the arm-soc cleanup2 branch, while the irqdomain tree will be sent
by Grant before this one gets integrated.

Conflicts:
	drivers/rtc/rtc-at91sam9.c
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 590d829a 280ad7fd 7eca30ae
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Showing with 3450 additions and 5544 deletions
Documentation/IRQ-domain.txt 0 → 100644
View file @ 6e1d521b
irq_domain interrupt number mapping library
The current design of the Linux kernel uses a single large number
space where each separate IRQ source is assigned a different number.
This is simple when there is only one interrupt controller, but in
systems with multiple interrupt controllers the kernel must ensure
that each one gets assigned non-overlapping allocations of Linux
IRQ numbers.
The irq_alloc_desc*() and irq_free_desc*() APIs provide allocation of
irq numbers, but they don't provide any support for reverse mapping of
the controller-local IRQ (hwirq) number into the Linux IRQ number
space.
The irq_domain library adds mapping between hwirq and IRQ numbers on
top of the irq_alloc_desc*() API. An irq_domain to manage mapping is
preferred over interrupt controller drivers open coding their own
reverse mapping scheme.
irq_domain also implements translation from Device Tree interrupt
specifiers to hwirq numbers, and can be easily extended to support
other IRQ topology data sources.
=== irq_domain usage ===
An interrupt controller driver creates and registers an irq_domain by
calling one of the irq_domain_add_*() functions (each mapping method
has a different allocator function, more on that later). The function
will return a pointer to the irq_domain on success. The caller must
provide the allocator function with an irq_domain_ops structure with
the .map callback populated as a minimum.
In most cases, the irq_domain will begin empty without any mappings
between hwirq and IRQ numbers. Mappings are added to the irq_domain
by calling irq_create_mapping() which accepts the irq_domain and a
hwirq number as arguments. If a mapping for the hwirq doesn't already
exist then it will allocate a new Linux irq_desc, associate it with
the hwirq, and call the .map() callback so the driver can perform any
required hardware setup.
When an interrupt is received, irq_find_mapping() function should
be used to find the Linux IRQ number from the hwirq number.
If the driver has the Linux IRQ number or the irq_data pointer, and
needs to know the associated hwirq number (such as in the irq_chip
callbacks) then it can be directly obtained from irq_data->hwirq.
=== Types of irq_domain mappings ===
There are several mechanisms available for reverse mapping from hwirq
to Linux irq, and each mechanism uses a different allocation function.
Which reverse map type should be used depends on the use case. Each
of the reverse map types are described below:
==== Linear ====
irq_domain_add_linear()
The linear reverse map maintains a fixed size table indexed by the
hwirq number. When a hwirq is mapped, an irq_desc is allocated for
the hwirq, and the IRQ number is stored in the table.
The Linear map is a good choice when the maximum number of hwirqs is
fixed and a relatively small number (~ < 256). The advantages of this
map are fixed time lookup for IRQ numbers, and irq_descs are only
allocated for in-use IRQs. The disadvantage is that the table must be
as large as the largest possible hwirq number.
The majority of drivers should use the linear map.
==== Tree ====
irq_domain_add_tree()
The irq_domain maintains a radix tree map from hwirq numbers to Linux
IRQs. When an hwirq is mapped, an irq_desc is allocated and the
hwirq is used as the lookup key for the radix tree.
The tree map is a good choice if the hwirq number can be very large
since it doesn't need to allocate a table as large as the largest
hwirq number. The disadvantage is that hwirq to IRQ number lookup is
dependent on how many entries are in the table.
Very few drivers should need this mapping. At the moment, powerpc
iseries is the only user.
==== No Map ===-
irq_domain_add_nomap()
The No Map mapping is to be used when the hwirq number is
programmable in the hardware. In this case it is best to program the
Linux IRQ number into the hardware itself so that no mapping is
required. Calling irq_create_direct_mapping() will allocate a Linux
IRQ number and call the .map() callback so that driver can program the
Linux IRQ number into the hardware.
Most drivers cannot use this mapping.
==== Legacy ====
irq_domain_add_legacy()
irq_domain_add_legacy_isa()
The Legacy mapping is a special case for drivers that already have a
range of irq_descs allocated for the hwirqs. It is used when the
driver cannot be immediately converted to use the linear mapping. For
example, many embedded system board support files use a set of #defines
for IRQ numbers that are passed to struct device registrations. In that
case the Linux IRQ numbers cannot be dynamically assigned and the legacy
mapping should be used.
The legacy map assumes a contiguous range of IRQ numbers has already
been allocated for the controller and that the IRQ number can be
calculated by adding a fixed offset to the hwirq number, and
visa-versa. The disadvantage is that it requires the interrupt
controller to manage IRQ allocations and it requires an irq_desc to be
allocated for every hwirq, even if it is unused.
The legacy map should only be used if fixed IRQ mappings must be
supported. For example, ISA controllers would use the legacy map for
mapping Linux IRQs 0-15 so that existing ISA drivers get the correct IRQ
numbers.
Documentation/feature-removal-schedule.txt
View file @ 6e1d521b
......@@ -510,17 +510,3 @@ Why: The pci_scan_bus_parented() interface creates a new root bus. The
convert to using pci_scan_root_bus() so they can supply a list of
bus resources when the bus is created.
Who: Bjorn Helgaas <bhelgaas@google.com>
----------------------------
What: The CAP9 SoC family will be removed
When: 3.4
Files: arch/arm/mach-at91/at91cap9.c
arch/arm/mach-at91/at91cap9_devices.c
arch/arm/mach-at91/include/mach/at91cap9.h
arch/arm/mach-at91/include/mach/at91cap9_matrix.h
arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
arch/arm/mach-at91/board-cap9adk.c
Why: The code is not actively maintained and platforms are now hard to find.
Who: Nicolas Ferre <nicolas.ferre@atmel.com>
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
MAINTAINERS
View file @ 6e1d521b
......@@ -3638,6 +3638,15 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
F: kernel/irq/
IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY)
M: Benjamin Herrenschmidt <benh@kernel.crashing.org>
M: Grant Likely <grant.likely@secretlab.ca>
T: git git://git.secretlab.ca/git/linux-2.6.git irqdomain/next
S: Maintained
F: Documentation/IRQ-domain.txt
F: include/linux/irqdomain.h
F: kernel/irq/irqdomain.c
ISAPNP
M: Jaroslav Kysela <perex@perex.cz>
S: Maintained
......
arch/arm/Kconfig
View file @ 6e1d521b
......@@ -324,7 +324,7 @@ config ARCH_AT91
select CLKDEV_LOOKUP
help
This enables support for systems based on the Atmel AT91RM9200,
AT91SAM9 and AT91CAP9 processors.
AT91SAM9 processors.
config ARCH_BCMRING
bool "Broadcom BCMRING"
......
arch/arm/Kconfig.debug
View file @ 6e1d521b
......@@ -86,7 +86,7 @@ choice
depends on HAVE_AT91_DBGU0
config AT91_DEBUG_LL_DBGU1
bool "Kernel low-level debugging on 9263, 9g45 and cap9"
bool "Kernel low-level debugging on 9263 and 9g45"
depends on HAVE_AT91_DBGU1
config DEBUG_CLPS711X_UART1
......
arch/arm/boot/dts/at91sam9g25ek.dts 0 → 100644
View file @ 6e1d521b
/*
* at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
*
* Copyright (C) 2012 Atmel,
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
/include/ "at91sam9x5.dtsi"
/include/ "at91sam9x5cm.dtsi"
/ {
model = "Atmel AT91SAM9G25-EK";
compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
chosen {
bootargs = "128M console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
};
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
usart0: serial@f801c000 {
status = "okay";
};
macb0: ethernet@f802c000 {
phy-mode = "rmii";
status = "okay";
};
};
};
};
arch/arm/boot/dts/at91sam9x5.dtsi 0 → 100644
View file @ 6e1d521b
/*
* at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
* applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
* AT91SAM9X25, AT91SAM9X35 SoC
*
* Copyright (C) 2012 Atmel,
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/include/ "skeleton.dtsi"
/ {
model = "Atmel AT91SAM9x5 family SoC";
compatible = "atmel,at91sam9x5";
interrupt-parent = <&aic>;
aliases {
serial0 = &dbgu;
serial1 = &usart0;
serial2 = &usart1;
serial3 = &usart2;
gpio0 = &pioA;
gpio1 = &pioB;
gpio2 = &pioC;
gpio3 = &pioD;
tcb0 = &tcb0;
tcb1 = &tcb1;
};
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
};
};
memory@20000000 {
reg = <0x20000000 0x10000000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
aic: interrupt-controller@fffff000 {
#interrupt-cells = <2>;
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
interrupt-parent;
reg = <0xfffff000 0x200>;
};
pit: timer@fffffe30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 4>;
};
tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 4>;
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 4>;
};
dma0: dma-controller@ffffec00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <20 4>;
};
dma1: dma-controller@ffffee00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffee00 0x200>;
interrupts = <21 4>;
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x100>;
interrupts = <2 4>;
#gpio-cells = <2>;
gpio-controller;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x100>;
interrupts = <2 4>;
#gpio-cells = <2>;
gpio-controller;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x100>;
interrupts = <3 4>;
#gpio-cells = <2>;
gpio-controller;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x100>;
interrupts = <3 4>;
#gpio-cells = <2>;
gpio-controller;
};
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
interrupts = <1 4>;
status = "disabled";
};
usart0: serial@f801c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf801c000 0x200>;
interrupts = <5 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart1: serial@f8020000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8020000 0x200>;
interrupts = <6 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart2: serial@f8024000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8024000 0x200>;
interrupts = <7 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
macb0: ethernet@f802c000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
interrupts = <24 4>;
status = "disabled";
};
macb1: ethernet@f8030000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xf8030000 0x100>;
interrupts = <27 4>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/at91sam9x5cm.dtsi 0 → 100644
View file @ 6e1d521b
/*
* at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
*
* Copyright (C) 2012 Atmel,
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/ {
memory@20000000 {
reg = <0x20000000 0x8000000>;
};
};
arch/arm/common/gic.c
View file @ 6e1d521b
......@@ -51,7 +51,6 @@ union gic_base {
};
struct gic_chip_data {
unsigned int irq_offset;
union gic_base dist_base;
union gic_base cpu_base;
#ifdef CONFIG_CPU_PM
......@@ -61,9 +60,7 @@ struct gic_chip_data {
u32 __percpu *saved_ppi_enable;
u32 __percpu *saved_ppi_conf;
#endif
#ifdef CONFIG_IRQ_DOMAIN
struct irq_domain domain;
#endif
struct irq_domain *domain;
unsigned int gic_irqs;
#ifdef CONFIG_GIC_NON_BANKED
void __iomem *(*get_base)(union gic_base *);
......@@ -282,7 +279,7 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
irqnr = irqstat & ~0x1c00;
if (likely(irqnr > 15 && irqnr < 1021)) {
irqnr = irq_domain_to_irq(&gic->domain, irqnr);
irqnr = irq_find_mapping(gic->domain, irqnr);
handle_IRQ(irqnr, regs);
continue;
}
......@@ -314,8 +311,8 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
if (gic_irq == 1023)
goto out;
cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq);
if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
if (unlikely(gic_irq < 32 || gic_irq > 1020))
do_bad_IRQ(cascade_irq, desc);
else
generic_handle_irq(cascade_irq);
......@@ -348,10 +345,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
static void __init gic_dist_init(struct gic_chip_data *gic)
{
unsigned int i, irq;
unsigned int i;
u32 cpumask;
unsigned int gic_irqs = gic->gic_irqs;
struct irq_domain *domain = &gic->domain;
void __iomem *base = gic_data_dist_base(gic);
u32 cpu = cpu_logical_map(smp_processor_id());
......@@ -386,23 +382,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
for (i = 32; i < gic_irqs; i += 32)
writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
/*
* Setup the Linux IRQ subsystem.
*/
irq_domain_for_each_irq(domain, i, irq) {
if (i < 32) {
irq_set_percpu_devid(irq);
irq_set_chip_and_handler(irq, &gic_chip,
handle_percpu_devid_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
} else {
irq_set_chip_and_handler(irq, &gic_chip,
handle_fasteoi_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
irq_set_chip_data(irq, gic);
}
writel_relaxed(1, base + GIC_DIST_CTRL);
}
......@@ -618,11 +597,27 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
}
#endif
#ifdef CONFIG_OF
static int gic_irq_domain_dt_translate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq, unsigned int *out_type)
static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
if (hw < 32) {
irq_set_percpu_devid(irq);
irq_set_chip_and_handler(irq, &gic_chip,
handle_percpu_devid_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
} else {
irq_set_chip_and_handler(irq, &gic_chip,
handle_fasteoi_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
irq_set_chip_data(irq, d->host_data);
return 0;
}
static int gic_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq, unsigned int *out_type)
{
if (d->of_node != controller)
return -EINVAL;
......@@ -639,26 +634,23 @@ static int gic_irq_domain_dt_translate(struct irq_domain *d,
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
return 0;
}
#endif
const struct irq_domain_ops gic_irq_domain_ops = {
#ifdef CONFIG_OF
.dt_translate = gic_irq_domain_dt_translate,
#endif
.map = gic_irq_domain_map,
.xlate = gic_irq_domain_xlate,
};
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
void __iomem *dist_base, void __iomem *cpu_base,
u32 percpu_offset)
u32 percpu_offset, struct device_node *node)
{
irq_hw_number_t hwirq_base;
struct gic_chip_data *gic;
struct irq_domain *domain;
int gic_irqs;
int gic_irqs, irq_base;
BUG_ON(gic_nr >= MAX_GIC_NR);
gic = &gic_data[gic_nr];
domain = &gic->domain;
#ifdef CONFIG_GIC_NON_BANKED
if (percpu_offset) { /* Frankein-GIC without banked registers... */
unsigned int cpu;
......@@ -694,10 +686,10 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
* For primary GICs, skip over SGIs.
* For secondary GICs, skip over PPIs, too.
*/
domain->hwirq_base = 32;
hwirq_base = 32;
if (gic_nr == 0) {
if ((irq_start & 31) > 0) {
domain->hwirq_base = 16;
hwirq_base = 16;
if (irq_start != -1)
irq_start = (irq_start & ~31) + 16;
}
......@@ -713,17 +705,17 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
gic_irqs = 1020;
gic->gic_irqs = gic_irqs;
domain->nr_irq = gic_irqs - domain->hwirq_base;
domain->irq_base = irq_alloc_descs(irq_start, 16, domain->nr_irq,
numa_node_id());
if (IS_ERR_VALUE(domain->irq_base)) {
gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
if (IS_ERR_VALUE(irq_base)) {
WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
irq_start);
domain->irq_base = irq_start;
irq_base = irq_start;
}
domain->priv = gic;
domain->ops = &gic_irq_domain_ops;
irq_domain_add(domain);
gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
hwirq_base, &gic_irq_domain_ops, gic);
if (WARN_ON(!gic->domain))
return;
gic_chip.flags |= gic_arch_extn.flags;
gic_dist_init(gic);
......@@ -768,7 +760,6 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
void __iomem *dist_base;
u32 percpu_offset;
int irq;
struct irq_domain *domain = &gic_data[gic_cnt].domain;
if (WARN_ON(!node))
return -ENODEV;
......@@ -782,9 +773,7 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
percpu_offset = 0;
domain->of_node = of_node_get(node);
gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset);
gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
if (parent) {
irq = irq_of_parse_and_map(node, 0);
......
arch/arm/common/vic.c
View file @ 6e1d521b
......@@ -56,7 +56,7 @@ struct vic_device {
u32 int_enable;
u32 soft_int;
u32 protect;
struct irq_domain domain;
struct irq_domain *domain;
};
/* we cannot allocate memory when VICs are initially registered */
......@@ -192,14 +192,8 @@ static void __init vic_register(void __iomem *base, unsigned int irq,
v->resume_sources = resume_sources;
v->irq = irq;
vic_id++;
v->domain.irq_base = irq;
v->domain.nr_irq = 32;
#ifdef CONFIG_OF_IRQ
v->domain.of_node = of_node_get(node);
#endif /* CONFIG_OF */
v->domain.ops = &irq_domain_simple_ops;
irq_domain_add(&v->domain);
v->domain = irq_domain_add_legacy(node, 32, irq, 0,
&irq_domain_simple_ops, v);
}
static void vic_ack_irq(struct irq_data *d)
......@@ -348,7 +342,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
vic_register(base, irq_start, 0, node);
}
static void __init __vic_init(void __iomem *base, unsigned int irq_start,
void __init __vic_init(void __iomem *base, unsigned int irq_start,
u32 vic_sources, u32 resume_sources,
struct device_node *node)
{
......@@ -444,7 +438,7 @@ static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
while (stat) {
irq = ffs(stat) - 1;
handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
stat &= ~(1 << irq);
handled = 1;
}
......
arch/arm/configs/at91cap9_defconfig deleted 100644 → 0
View file @ 590d829a
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91CAP9=y
CONFIG_MACH_AT91CAP9ADK=y
CONFIG_MTD_AT91_DATAFLASH_CARD=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
# CONFIG_ARM_THUMB is not set
CONFIG_AEABI=y
CONFIG_LEDS=y
CONFIG_LEDS_CPU=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/ram0 rw"
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_MACB=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
# CONFIG_SERIO is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_SPI=y
CONFIG_SPI_ATMEL=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_FB=y
CONFIG_FB_ATMEL=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETH=m
CONFIG_USB_FILE_STORAGE=m
CONFIG_MMC=y
CONFIG_MMC_AT91=m
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AT91SAM9=y
CONFIG_EXT2_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_USER=y
arch/arm/include/asm/hardware/gic.h
View file @ 6e1d521b
......@@ -39,7 +39,7 @@ struct device_node;
extern struct irq_chip gic_arch_extn;
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset);
u32 offset, struct device_node *);
int gic_of_init(struct device_node *node, struct device_node *parent);
void gic_secondary_init(unsigned int);
void gic_handle_irq(struct pt_regs *regs);
......@@ -49,7 +49,7 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
static inline void gic_init(unsigned int nr, int start,
void __iomem *dist , void __iomem *cpu)
{
gic_init_bases(nr, start, dist, cpu, 0);
gic_init_bases(nr, start, dist, cpu, 0, NULL);
}
#endif
......
arch/arm/include/asm/hardware/vic.h
View file @ 6e1d521b
......@@ -47,6 +47,8 @@
struct device_node;
struct pt_regs;
void __vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources,
u32 resume_sources, struct device_node *node);
void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
int vic_of_init(struct device_node *node, struct device_node *parent);
void vic_handle_irq(struct pt_regs *regs);
......
arch/arm/mach-at91/Kconfig
View file @ 6e1d521b
......@@ -102,13 +102,13 @@ config ARCH_AT91SAM9G45
select HAVE_AT91_DBGU1
select AT91_SAM9G45_RESET
config ARCH_AT91CAP9
bool "AT91CAP9"
config ARCH_AT91SAM9X5
bool "AT91SAM9x5 family"
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select HAVE_FB_ATMEL
select HAVE_NET_MACB
select HAVE_AT91_DBGU1
select HAVE_AT91_DBGU0
select AT91_SAM9G45_RESET
config ARCH_AT91X40
......@@ -447,21 +447,6 @@ endif
# ----------------------------------------------------------
if ARCH_AT91CAP9
comment "AT91CAP9 Board Type"
config MACH_AT91CAP9ADK
bool "Atmel AT91CAP9A-DK Evaluation Kit"
select HAVE_AT91_DATAFLASH_CARD
help
Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit.
<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138>
endif
# ----------------------------------------------------------
if ARCH_AT91X40
comment "AT91X40 Board Type"
......@@ -544,7 +529,7 @@ config AT91_EARLY_DBGU0
depends on HAVE_AT91_DBGU0
config AT91_EARLY_DBGU1
bool "DBGU on 9263, 9g45 and cap9"
bool "DBGU on 9263 and 9g45"
depends on HAVE_AT91_DBGU1
config AT91_EARLY_USART0
......
arch/arm/mach-at91/Makefile
View file @ 6e1d521b
......@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_d
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
# AT91RM9200 board-specific support
......@@ -81,9 +81,6 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
# AT91SAM board with device-tree
obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
# AT91CAP9 board-specific support
obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
# AT91X40 board-specific support
obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
......
arch/arm/mach-at91/Makefile.boot
View file @ 6e1d521b
......@@ -3,11 +3,7 @@
# PARAMS_PHYS must be within 4MB of ZRELADDR
# INITRD_PHYS must be in RAM
ifeq ($(CONFIG_ARCH_AT91CAP9),y)
zreladdr-y += 0x70008000
params_phys-y := 0x70000100
initrd_phys-y := 0x70410000
else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
zreladdr-y += 0x70008000
params_phys-y := 0x70000100
initrd_phys-y := 0x70410000
......@@ -17,4 +13,10 @@ params_phys-y := 0x20000100
initrd_phys-y := 0x20410000
endif
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb
# Keep dtb files sorted alphabetically for each SoC
# sam9g20
dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
# sam9g45
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
# sam9x5
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
arch/arm/mach-at91/at91cap9_devices.c deleted 100644 → 0
View file @ 590d829a
This diff is collapsed.
arch/arm/mach-at91/at91rm9200.c
View file @ 6e1d521b
......@@ -295,7 +295,7 @@ static void at91rm9200_idle(void)
* Disable the processor clock. The processor will be automatically
* re-enabled by an interrupt or by a reset.
*/
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
}
static void at91rm9200_restart(char mode, const char *cmd)
......@@ -303,8 +303,8 @@ static void at91rm9200_restart(char mode, const char *cmd)
/*
* Perform a hardware reset with the use of the Watchdog timer.
*/
at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
}
/* --------------------------------------------------------------------
......@@ -319,6 +319,8 @@ static void __init at91rm9200_map_io(void)
static void __init at91rm9200_ioremap_registers(void)
{
at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
}
static void __init at91rm9200_initialize(void)
......
arch/arm/mach-at91/at91rm9200_devices.c
View file @ 6e1d521b
......@@ -21,6 +21,7 @@
#include <mach/board.h>
#include <mach/at91rm9200.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include "generic.h"
......@@ -241,15 +242,15 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
data->chipselect = 4; /* can only use EBI ChipSelect 4 */
/* CF takes over CS4, CS5, CS6 */
csa = at91_sys_read(AT91_EBI_CSA);
at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
csa = at91_ramc_read(0, AT91_EBI_CSA);
at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
/*
* Static memory controller timing adjustments.
* REVISIT: these timings are in terms of MCK cycles, so
* when MCK changes (cpufreq etc) so must these values...
*/
at91_sys_write(AT91_SMC_CSR(4),
at91_ramc_write(0, AT91_SMC_CSR(4),
AT91_SMC_ACSS_STD
| AT91_SMC_DBW_16
| AT91_SMC_BAT
......@@ -407,11 +408,11 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
return;
/* enable the address range of CS3 */
csa = at91_sys_read(AT91_EBI_CSA);
at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
csa = at91_ramc_read(0, AT91_EBI_CSA);
at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
/* set the bus interface characteristics */
at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
| AT91_SMC_NWS_(5)
| AT91_SMC_TDF_(1)
| AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
......@@ -1114,7 +1115,6 @@ static inline void configure_usart3_pins(unsigned pins)
}
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
......
arch/arm/mach-at91/at91rm9200_time.c
View file @ 6e1d521b
......@@ -43,9 +43,9 @@ static inline unsigned long read_CRTR(void)
{
unsigned long x1, x2;
x1 = at91_sys_read(AT91_ST_CRTR);
x1 = at91_st_read(AT91_ST_CRTR);
do {
x2 = at91_sys_read(AT91_ST_CRTR);
x2 = at91_st_read(AT91_ST_CRTR);
if (x1 == x2)
break;
x1 = x2;
......@@ -58,7 +58,7 @@ static inline unsigned long read_CRTR(void)
*/
static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
{
u32 sr = at91_sys_read(AT91_ST_SR) & irqmask;
u32 sr = at91_st_read(AT91_ST_SR) & irqmask;
/*
* irqs should be disabled here, but as the irq is shared they are only
......@@ -110,22 +110,22 @@ static void
clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
{
/* Disable and flush pending timer interrupts */
at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
(void) at91_sys_read(AT91_ST_SR);
at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
at91_st_read(AT91_ST_SR);
last_crtr = read_CRTR();
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
/* PIT for periodic irqs; fixed rate of 1/HZ */
irqmask = AT91_ST_PITS;
at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* ALM for oneshot irqs, set by next_event()
* before 32 seconds have passed
*/
irqmask = AT91_ST_ALMS;
at91_sys_write(AT91_ST_RTAR, last_crtr);
at91_st_write(AT91_ST_RTAR, last_crtr);
break;
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_UNUSED:
......@@ -133,7 +133,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
irqmask = 0;
break;
}
at91_sys_write(AT91_ST_IER, irqmask);
at91_st_write(AT91_ST_IER, irqmask);
}
static int
......@@ -156,12 +156,12 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
alm = read_CRTR();
/* Cancel any pending alarm; flush any pending IRQ */
at91_sys_write(AT91_ST_RTAR, alm);
(void) at91_sys_read(AT91_ST_SR);
at91_st_write(AT91_ST_RTAR, alm);
at91_st_read(AT91_ST_SR);
/* Schedule alarm by writing RTAR. */
alm += delta;
at91_sys_write(AT91_ST_RTAR, alm);
at91_st_write(AT91_ST_RTAR, alm);
return status;
}
......@@ -175,15 +175,24 @@ static struct clock_event_device clkevt = {
.set_mode = clkevt32k_mode,
};
void __iomem *at91_st_base;
void __init at91rm9200_ioremap_st(u32 addr)
{
at91_st_base = ioremap(addr, 256);
if (!at91_st_base)
panic("Impossible to ioremap ST\n");
}
/*
* ST (system timer) module supports both clockevents and clocksource.
*/
void __init at91rm9200_timer_init(void)
{
/* Disable all timer interrupts, and clear any pending ones */
at91_sys_write(AT91_ST_IDR,
at91_st_write(AT91_ST_IDR,
AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
(void) at91_sys_read(AT91_ST_SR);
at91_st_read(AT91_ST_SR);
/* Make IRQs happen for the system timer */
setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
......@@ -192,7 +201,7 @@ void __init at91rm9200_timer_init(void)
* directly for the clocksource and all clockevents, after adjusting
* its prescaler from the 1 Hz default.
*/
at91_sys_write(AT91_ST_RTMR, 1);
at91_st_write(AT91_ST_RTMR, 1);
/* Setup timer clockevent, with minimum of two ticks (important!!) */
clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
......
arch/arm/mach-at91/at91sam9260.c
View file @ 6e1d521b
......@@ -310,34 +310,27 @@ static void __init at91sam9xe_map_io(void)
static void __init at91sam9260_map_io(void)
{
if (cpu_is_at91sam9xe()) {
if (cpu_is_at91sam9xe())
at91sam9xe_map_io();
} else if (cpu_is_at91sam9g20()) {
at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE);
at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE);
} else {
at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
}
else if (cpu_is_at91sam9g20())
at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
else
at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
}
static void __init at91sam9260_ioremap_registers(void)
{
at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
}
static void at91sam9260_idle(void)
{
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
cpu_do_idle();
at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
}
static void __init at91sam9260_initialize(void)
{
arm_pm_idle = at91sam9260_idle;
arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);
......
arch/arm/mach-at91/at91sam9260_devices.c
View file @ 6e1d521b
......@@ -21,6 +21,7 @@
#include <mach/cpu.h>
#include <mach/at91sam9260.h>
#include <mach/at91sam9260_matrix.h>
#include <mach/at91_matrix.h>
#include <mach/at91sam9_smc.h>
#include "generic.h"
......@@ -422,8 +423,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
......@@ -717,18 +718,42 @@ static struct resource rtt_resources[] = {
.start = AT91SAM9260_BASE_RTT,
.end = AT91SAM9260_BASE_RTT + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}
}, {
.flags = IORESOURCE_MEM,
},
};
static struct platform_device at91sam9260_rtt_device = {
.name = "at91_rtt",
.id = 0,
.resource = rtt_resources,
.num_resources = ARRAY_SIZE(rtt_resources),
};
#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
static void __init at91_add_device_rtt_rtc(void)
{
at91sam9260_rtt_device.name = "rtc-at91sam9";
/*
* The second resource is needed:
* GPBR will serve as the storage for RTC time offset
*/
at91sam9260_rtt_device.num_resources = 2;
rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
rtt_resources[1].end = rtt_resources[1].start + 3;
}
#else
static void __init at91_add_device_rtt_rtc(void)
{
/* Only one resource is needed: RTT not used as RTC */
at91sam9260_rtt_device.num_resources = 1;
}
#endif
static void __init at91_add_device_rtt(void)
{
at91_add_device_rtt_rtc();
platform_device_register(&at91sam9260_rtt_device);
}
......@@ -1139,7 +1164,6 @@ static inline void configure_usart5_pins(void)
}
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
......@@ -1264,7 +1288,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
if (!data)
return;
csa = at91_sys_read(AT91_MATRIX_EBICSA);
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
switch (data->chipselect) {
case 4:
......@@ -1287,7 +1311,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
return;
}
at91_sys_write(AT91_MATRIX_EBICSA, csa);
at91_matrix_write(AT91_MATRIX_EBICSA, csa);
if (gpio_is_valid(data->rst_pin)) {
at91_set_multi_drive(data->rst_pin, 0);
......
arch/arm/mach-at91/at91sam9261.c
View file @ 6e1d521b
......@@ -283,19 +283,15 @@ static void __init at91sam9261_ioremap_registers(void)
{
at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
}
static void at91sam9261_idle(void)
{
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
cpu_do_idle();
at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
}
static void __init at91sam9261_initialize(void)
{
arm_pm_idle = at91sam9261_idle;
arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart;
at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
| (1 << AT91SAM9261_ID_IRQ2);
......
arch/arm/mach-at91/at91sam9261_devices.c
View file @ 6e1d521b
......@@ -24,6 +24,7 @@
#include <mach/board.h>
#include <mach/at91sam9261.h>
#include <mach/at91sam9261_matrix.h>
#include <mach/at91_matrix.h>
#include <mach/at91sam9_smc.h>
#include "generic.h"
......@@ -236,8 +237,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
......@@ -603,6 +604,8 @@ static struct resource rtt_resources[] = {
.start = AT91SAM9261_BASE_RTT,
.end = AT91SAM9261_BASE_RTT + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}, {
.flags = IORESOURCE_MEM,
}
};
......@@ -610,11 +613,32 @@ static struct platform_device at91sam9261_rtt_device = {
.name = "at91_rtt",
.id = 0,
.resource = rtt_resources,
.num_resources = ARRAY_SIZE(rtt_resources),
};
#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
static void __init at91_add_device_rtt_rtc(void)
{
at91sam9261_rtt_device.name = "rtc-at91sam9";
/*
* The second resource is needed:
* GPBR will serve as the storage for RTC time offset
*/
at91sam9261_rtt_device.num_resources = 2;
rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
rtt_resources[1].end = rtt_resources[1].start + 3;
}
#else
static void __init at91_add_device_rtt_rtc(void)
{
/* Only one resource is needed: RTT not used as RTC */
at91sam9261_rtt_device.num_resources = 1;
}
#endif
static void __init at91_add_device_rtt(void)
{
at91_add_device_rtt_rtc();
platform_device_register(&at91sam9261_rtt_device);
}
......@@ -991,7 +1015,6 @@ static inline void configure_usart2_pins(unsigned pins)
}
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
......
arch/arm/mach-at91/at91sam9263.c
View file @ 6e1d521b
......@@ -303,20 +303,17 @@ static void __init at91sam9263_ioremap_registers(void)
{
at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
}
static void at91sam9263_idle(void)
{
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
cpu_do_idle();
at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
}
static void __init at91sam9263_initialize(void)
{
arm_pm_idle = at91sam9263_idle;
arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart;
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
......
arch/arm/mach-at91/at91sam9263_devices.c
View file @ 6e1d521b
......@@ -23,6 +23,7 @@
#include <mach/board.h>
#include <mach/at91sam9263.h>
#include <mach/at91sam9263_matrix.h>
#include <mach/at91_matrix.h>
#include <mach/at91sam9_smc.h>
#include "generic.h"
......@@ -409,7 +410,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
* we assume SMC timings are configured by board code,
* except True IDE where timings are controlled by driver
*/
ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
switch (data->chipselect) {
case 4:
at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
......@@ -428,7 +429,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
data->chipselect);
return;
}
at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
if (gpio_is_valid(data->det_pin)) {
at91_set_gpio_input(data->det_pin, 1);
......@@ -496,8 +497,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
......@@ -891,7 +892,8 @@ static struct platform_device at91sam9263_isi_device = {
.num_resources = ARRAY_SIZE(isi_resources),
};
void __init at91_add_device_isi(void)
void __init at91_add_device_isi(struct isi_platform_data *data,
bool use_pck_as_mck)
{
at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
......@@ -904,14 +906,20 @@ void __init at91_add_device_isi(void)
at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
if (use_pck_as_mck) {
at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
/* TODO: register the PCK for ISI_MCK and set its parent */
}
}
#else
void __init at91_add_device_isi(void) {}
void __init at91_add_device_isi(struct isi_platform_data *data,
bool use_pck_as_mck) {}
#endif
......@@ -959,6 +967,8 @@ static struct resource rtt0_resources[] = {
.start = AT91SAM9263_BASE_RTT0,
.end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}, {
.flags = IORESOURCE_MEM,
}
};
......@@ -966,7 +976,6 @@ static struct platform_device at91sam9263_rtt0_device = {
.name = "at91_rtt",
.id = 0,
.resource = rtt0_resources,
.num_resources = ARRAY_SIZE(rtt0_resources),
};
static struct resource rtt1_resources[] = {
......@@ -974,6 +983,8 @@ static struct resource rtt1_resources[] = {
.start = AT91SAM9263_BASE_RTT1,
.end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}, {
.flags = IORESOURCE_MEM,
}
};
......@@ -981,11 +992,53 @@ static struct platform_device at91sam9263_rtt1_device = {
.name = "at91_rtt",
.id = 1,
.resource = rtt1_resources,
.num_resources = ARRAY_SIZE(rtt1_resources),
};
#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
static void __init at91_add_device_rtt_rtc(void)
{
struct platform_device *pdev;
struct resource *r;
switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
case 0:
/*
* The second resource is needed only for the chosen RTT:
* GPBR will serve as the storage for RTC time offset
*/
at91sam9263_rtt0_device.num_resources = 2;
at91sam9263_rtt1_device.num_resources = 1;
pdev = &at91sam9263_rtt0_device;
r = rtt0_resources;
break;
case 1:
at91sam9263_rtt0_device.num_resources = 1;
at91sam9263_rtt1_device.num_resources = 2;
pdev = &at91sam9263_rtt1_device;
r = rtt1_resources;
break;
default:
pr_err("at91sam9263: only supports 2 RTT (%d)\n",
CONFIG_RTC_DRV_AT91SAM9_RTT);
return;
}
pdev->name = "rtc-at91sam9";
r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
r[1].end = r[1].start + 3;
}
#else
static void __init at91_add_device_rtt_rtc(void)
{
/* Only one resource is needed: RTT not used as RTC */
at91sam9263_rtt0_device.num_resources = 1;
at91sam9263_rtt1_device.num_resources = 1;
}
#endif
static void __init at91_add_device_rtt(void)
{
at91_add_device_rtt_rtc();
platform_device_register(&at91sam9263_rtt0_device);
platform_device_register(&at91sam9263_rtt1_device);
}
......@@ -1371,7 +1424,6 @@ static inline void configure_usart2_pins(unsigned pins)
}
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
......
arch/arm/mach-at91/at91sam9_alt_reset.S
View file @ 6e1d521b
......@@ -15,16 +15,17 @@
#include <linux/linkage.h>
#include <mach/hardware.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91_ramc.h>
#include <mach/at91_rstc.h>
.arm
.globl at91sam9_alt_restart
at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
ldr r1, =at91_rstc_base
ldr r1, [r1]
at91sam9_alt_restart: ldr r0, =at91_ramc_base @ preload constants
ldr r0, [r0]
ldr r4, =at91_rstc_base
ldr r1, [r4]
mov r2, #1
mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
......@@ -37,6 +38,3 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
str r4, [r1, #AT91_RSTC_CR] @ reset processor
b .
.at91_va_base_sdramc:
.word AT91_VA_BASE_SYS + AT91_SDRAMC0
arch/arm/mach-at91/at91sam9g45.c
View file @ 6e1d521b
......@@ -317,12 +317,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
}
};
static void at91sam9g45_idle(void)
{
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
cpu_do_idle();
}
/* --------------------------------------------------------------------
* AT91SAM9G45 processor initialization
* -------------------------------------------------------------------- */
......@@ -337,13 +331,16 @@ static void __init at91sam9g45_ioremap_registers(void)
{
at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
}
static void __init at91sam9g45_initialize(void)
{
arm_pm_idle = at91sam9g45_idle;
arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9g45_restart;
at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
......
arch/arm/mach-at91/at91sam9g45_devices.c
View file @ 6e1d521b
......@@ -14,6 +14,7 @@
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/i2c-gpio.h>
#include <linux/atmel-mci.h>
......@@ -24,11 +25,15 @@
#include <mach/board.h>
#include <mach/at91sam9g45.h>
#include <mach/at91sam9g45_matrix.h>
#include <mach/at91_matrix.h>
#include <mach/at91sam9_smc.h>
#include <mach/at_hdmac.h>
#include <mach/atmel-mci.h>
#include <media/atmel-isi.h>
#include "generic.h"
#include "clock.h"
/* --------------------------------------------------------------------
......@@ -38,10 +43,6 @@
#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
static u64 hdmac_dmamask = DMA_BIT_MASK(32);
static struct at_dma_platform_data atdma_pdata = {
.nr_channels = 8,
};
static struct resource hdmac_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_DMA,
......@@ -56,12 +57,11 @@ static struct resource hdmac_resources[] = {
};
static struct platform_device at_hdmac_device = {
.name = "at_hdmac",
.name = "at91sam9g45_dma",
.id = -1,
.dev = {
.dma_mask = &hdmac_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &atdma_pdata,
},
.resource = hdmac_resources,
.num_resources = ARRAY_SIZE(hdmac_resources),
......@@ -69,9 +69,15 @@ static struct platform_device at_hdmac_device = {
void __init at91_add_device_hdmac(void)
{
dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
platform_device_register(&at_hdmac_device);
#if defined(CONFIG_OF)
struct device_node *of_node =
of_find_node_by_name(NULL, "dma-controller");
if (of_node)
of_node_put(of_node);
else
#endif
platform_device_register(&at_hdmac_device);
}
#else
void __init at91_add_device_hdmac(void) {}
......@@ -552,8 +558,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
......@@ -869,6 +875,96 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
#endif
/* --------------------------------------------------------------------
* Image Sensor Interface
* -------------------------------------------------------------------- */
#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
static u64 isi_dmamask = DMA_BIT_MASK(32);
static struct isi_platform_data isi_data;
struct resource isi_resources[] = {
[0] = {
.start = AT91SAM9G45_BASE_ISI,
.end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91SAM9G45_ID_ISI,
.end = AT91SAM9G45_ID_ISI,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device at91sam9g45_isi_device = {
.name = "atmel_isi",
.id = 0,
.dev = {
.dma_mask = &isi_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &isi_data,
},
.resource = isi_resources,
.num_resources = ARRAY_SIZE(isi_resources),
};
static struct clk_lookup isi_mck_lookups[] = {
CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
};
void __init at91_add_device_isi(struct isi_platform_data *data,
bool use_pck_as_mck)
{
struct clk *pck;
struct clk *parent;
if (!data)
return;
isi_data = *data;
at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */
at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */
at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */
at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */
at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */
at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */
at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */
at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */
at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */
at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */
at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */
at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */
at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */
at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */
platform_device_register(&at91sam9g45_isi_device);
if (use_pck_as_mck) {
at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */
pck = clk_get(NULL, "pck1");
parent = clk_get(NULL, "plla");
BUG_ON(IS_ERR(pck) || IS_ERR(parent));
if (clk_set_parent(pck, parent)) {
pr_err("Failed to set PCK's parent\n");
} else {
/* Register PCK as ISI_MCK */
isi_mck_lookups[0].clk = pck;
clkdev_add_table(isi_mck_lookups,
ARRAY_SIZE(isi_mck_lookups));
}
clk_put(pck);
clk_put(parent);
}
}
#else
void __init at91_add_device_isi(struct isi_platform_data *data,
bool use_pck_as_mck) {}
#endif
/* --------------------------------------------------------------------
* LCD Controller
......@@ -1098,6 +1194,8 @@ static struct resource rtt_resources[] = {
.start = AT91SAM9G45_BASE_RTT,
.end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}, {
.flags = IORESOURCE_MEM,
}
};
......@@ -1105,11 +1203,32 @@ static struct platform_device at91sam9g45_rtt_device = {
.name = "at91_rtt",
.id = 0,
.resource = rtt_resources,
.num_resources = ARRAY_SIZE(rtt_resources),
};
#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
static void __init at91_add_device_rtt_rtc(void)
{
at91sam9g45_rtt_device.name = "rtc-at91sam9";
/*
* The second resource is needed:
* GPBR will serve as the storage for RTC time offset
*/
at91sam9g45_rtt_device.num_resources = 2;
rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
rtt_resources[1].end = rtt_resources[1].start + 3;
}
#else
static void __init at91_add_device_rtt_rtc(void)
{
/* Only one resource is needed: RTT not used as RTC */
at91sam9g45_rtt_device.num_resources = 1;
}
#endif
static void __init at91_add_device_rtt(void)
{
at91_add_device_rtt_rtc();
platform_device_register(&at91sam9g45_rtt_device);
}
......@@ -1564,7 +1683,6 @@ static inline void configure_usart3_pins(unsigned pins)
}
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
......
arch/arm/mach-at91/at91sam9g45_reset.S
View file @ 6e1d521b
......@@ -12,7 +12,7 @@
#include <linux/linkage.h>
#include <mach/hardware.h>
#include <mach/at91sam9_ddrsdr.h>
#include <mach/at91_ramc.h>
#include <mach/at91_rstc.h>
.arm
......@@ -20,9 +20,10 @@
.globl at91sam9g45_restart
at91sam9g45_restart:
ldr r0, .at91_va_base_sdramc0 @ preload constants
ldr r1, =at91_rstc_base
ldr r1, [r1]
ldr r5, =at91_ramc_base @ preload constants
ldr r0, [r5]
ldr r4, =at91_rstc_base
ldr r1, [r4]
mov r2, #1
mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
......@@ -35,6 +36,3 @@ at91sam9g45_restart:
str r4, [r1, #AT91_RSTC_CR] @ reset processor
b .
.at91_va_base_sdramc0:
.word AT91_VA_BASE_SYS + AT91_DDRSDRC0
arch/arm/mach-at91/at91sam9rl.c
View file @ 6e1d521b
......@@ -288,19 +288,15 @@ static void __init at91sam9rl_ioremap_registers(void)
{
at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
}
static void at91sam9rl_idle(void)
{
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
cpu_do_idle();
at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
}
static void __init at91sam9rl_initialize(void)
{
arm_pm_idle = at91sam9rl_idle;
arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart;
at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
......
arch/arm/mach-at91/at91sam9rl_devices.c
View file @ 6e1d521b
......@@ -20,6 +20,7 @@
#include <mach/board.h>
#include <mach/at91sam9rl.h>
#include <mach/at91sam9rl_matrix.h>
#include <mach/at91_matrix.h>
#include <mach/at91sam9_smc.h>
#include <mach/at_hdmac.h>
......@@ -33,10 +34,6 @@
#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
static u64 hdmac_dmamask = DMA_BIT_MASK(32);
static struct at_dma_platform_data atdma_pdata = {
.nr_channels = 2,
};
static struct resource hdmac_resources[] = {
[0] = {
.start = AT91SAM9RL_BASE_DMA,
......@@ -51,12 +48,11 @@ static struct resource hdmac_resources[] = {
};
static struct platform_device at_hdmac_device = {
.name = "at_hdmac",
.name = "at91sam9rl_dma",
.id = -1,
.dev = {
.dma_mask = &hdmac_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &atdma_pdata,
},
.resource = hdmac_resources,
.num_resources = ARRAY_SIZE(hdmac_resources),
......@@ -64,7 +60,6 @@ static struct platform_device at_hdmac_device = {
void __init at91_add_device_hdmac(void)
{
dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
platform_device_register(&at_hdmac_device);
}
#else
......@@ -271,8 +266,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
......@@ -688,6 +683,8 @@ static struct resource rtt_resources[] = {
.start = AT91SAM9RL_BASE_RTT,
.end = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}, {
.flags = IORESOURCE_MEM,
}
};
......@@ -695,11 +692,32 @@ static struct platform_device at91sam9rl_rtt_device = {
.name = "at91_rtt",
.id = 0,
.resource = rtt_resources,
.num_resources = ARRAY_SIZE(rtt_resources),
};
#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
static void __init at91_add_device_rtt_rtc(void)
{
at91sam9rl_rtt_device.name = "rtc-at91sam9";
/*
* The second resource is needed:
* GPBR will serve as the storage for RTC time offset
*/
at91sam9rl_rtt_device.num_resources = 2;
rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
rtt_resources[1].end = rtt_resources[1].start + 3;
}
#else
static void __init at91_add_device_rtt_rtc(void)
{
/* Only one resource is needed: RTT not used as RTC */
at91sam9rl_rtt_device.num_resources = 1;
}
#endif
static void __init at91_add_device_rtt(void)
{
at91_add_device_rtt_rtc();
platform_device_register(&at91sam9rl_rtt_device);
}
......@@ -1134,7 +1152,6 @@ static inline void configure_usart3_pins(unsigned pins)
}
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
......
arch/arm/mach-at91/at91x40.c
View file @ 6e1d521b
......@@ -44,7 +44,7 @@ static void at91x40_idle(void)
* Disable the processor clock. The processor will be automatically
* re-enabled by an interrupt or by a reset.
*/
at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
__raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
cpu_do_idle();
}
......
arch/arm/mach-at91/at91x40_time.c
View file @ 6e1d521b
......@@ -28,6 +28,12 @@
#include <asm/mach/time.h>
#include <mach/at91_tc.h>
#define at91_tc_read(field) \
__raw_readl(AT91_TC + field)
#define at91_tc_write(field, value) \
__raw_writel(value, AT91_TC + field);
/*
* 3 counter/timer units present.
*/
......@@ -37,12 +43,12 @@
static unsigned long at91x40_gettimeoffset(void)
{
return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
}
static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
{
at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR);
at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
timer_tick();
return IRQ_HANDLED;
}
......@@ -57,20 +63,20 @@ void __init at91x40_timer_init(void)
{
unsigned int v;
at91_sys_write(AT91_TC + AT91_TC_BCR, 0);
v = at91_sys_read(AT91_TC + AT91_TC_BMR);
at91_tc_write(AT91_TC_BCR, 0);
v = at91_tc_read(AT91_TC_BMR);
v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
at91_sys_write(AT91_TC + AT91_TC_BMR, v);
at91_tc_write(AT91_TC_BMR, v);
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
}
struct sys_timer at91x40_timer = {
......
arch/arm/mach-at91/board-cap9adk.c deleted 100644 → 0
View file @ 590d829a
/*
* linux/arch/arm/mach-at91/board-cap9adk.c
*
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
* Copyright (C) 2005 SAN People
* Copyright (C) 2007 Atmel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/fb.h>
#include <linux/mtd/physmap.h>
#include <video/atmel_lcdc.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/board.h>
#include <mach/at91cap9_matrix.h>
#include <mach/at91sam9_smc.h>
#include <mach/system_rev.h>
#include "sam9_smc.h"
#include "generic.h"
static void __init cap9adk_init_early(void)
{
/* Initialize processor: 12 MHz crystal */
at91_initialize(12000000);
/* Setup the LEDs: USER1 and USER2 LED for cpu/timer... */
at91_init_leds(AT91_PIN_PA10, AT91_PIN_PA11);
/* ... POWER LED always on */
at91_set_gpio_output(AT91_PIN_PC29, 1);
/* Setup the serial ports and console */
at91_register_uart(0, 0, 0); /* DBGU = ttyS0 */
at91_set_serial_console(0);
}
/*
* USB Host port
*/
static struct at91_usbh_data __initdata cap9adk_usbh_data = {
.ports = 2,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
/*
* USB HS Device port
*/
static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
.vbus_pin = AT91_PIN_PB31,
};
/*
* ADS7846 Touchscreen
*/
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
static int ads7843_pendown_state(void)
{
return !at91_get_gpio_value(AT91_PIN_PC4); /* Touchscreen PENIRQ */
}
static struct ads7846_platform_data ads_info = {
.model = 7843,
.x_min = 150,
.x_max = 3830,
.y_min = 190,
.y_max = 3830,
.vref_delay_usecs = 100,
.x_plate_ohms = 450,
.y_plate_ohms = 250,
.pressure_max = 15000,
.debounce_max = 1,
.debounce_rep = 0,
.debounce_tol = (~0),
.get_pendown_state = ads7843_pendown_state,
};
static void __init cap9adk_add_device_ts(void)
{
at91_set_gpio_input(AT91_PIN_PC4, 1); /* Touchscreen PENIRQ */
at91_set_gpio_input(AT91_PIN_PC5, 1); /* Touchscreen BUSY */
}
#else
static void __init cap9adk_add_device_ts(void) {}
#endif
/*
* SPI devices.
*/
static struct spi_board_info cap9adk_spi_devices[] = {
#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
{ /* DataFlash card */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
},
#endif
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
{
.modalias = "ads7846",
.chip_select = 3, /* can be 2 or 3, depending on J2 jumper */
.max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
.bus_num = 0,
.platform_data = &ads_info,
.irq = AT91_PIN_PC4,
},
#endif
};
/*
* MCI (SD/MMC)
*/
static struct at91_mmc_data __initdata cap9adk_mmc_data = {
.wire4 = 1,
.det_pin = -EINVAL,
.wp_pin = -EINVAL,
.vcc_pin = -EINVAL,
};
/*
* MACB Ethernet device
*/
static struct macb_platform_data __initdata cap9adk_macb_data = {
.phy_irq_pin = -EINVAL,
.is_rmii = 1,
};
/*
* NAND flash
*/
static struct mtd_partition __initdata cap9adk_nand_partitions[] = {
{
.name = "NAND partition",
.offset = 0,
.size = MTDPART_SIZ_FULL,
},
};
static struct atmel_nand_data __initdata cap9adk_nand_data = {
.ale = 21,
.cle = 22,
.det_pin = -EINVAL,
.rdy_pin = -EINVAL,
.enable_pin = AT91_PIN_PD15,
.parts = cap9adk_nand_partitions,
.num_parts = ARRAY_SIZE(cap9adk_nand_partitions),
};
static struct sam9_smc_config __initdata cap9adk_nand_smc_config = {
.ncs_read_setup = 1,
.nrd_setup = 2,
.ncs_write_setup = 1,
.nwe_setup = 2,
.ncs_read_pulse = 6,
.nrd_pulse = 4,
.ncs_write_pulse = 6,
.nwe_pulse = 4,
.read_cycle = 8,
.write_cycle = 8,
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
.tdf_cycles = 1,
};
static void __init cap9adk_add_device_nand(void)
{
unsigned long csa;
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
cap9adk_nand_data.bus_width_16 = board_have_nand_16bit();
/* setup bus-width (8 or 16) */
if (cap9adk_nand_data.bus_width_16)
cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_16;
else
cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
sam9_smc_configure(0, 3, &cap9adk_nand_smc_config);
at91_add_device_nand(&cap9adk_nand_data);
}
/*
* NOR flash
*/
static struct mtd_partition cap9adk_nor_partitions[] = {
{
.name = "NOR partition",
.offset = 0,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data cap9adk_nor_data = {
.width = 2,
.parts = cap9adk_nor_partitions,
.nr_parts = ARRAY_SIZE(cap9adk_nor_partitions),
};
#define NOR_BASE AT91_CHIPSELECT_0
#define NOR_SIZE SZ_8M
static struct resource nor_flash_resources[] = {
{
.start = NOR_BASE,
.end = NOR_BASE + NOR_SIZE - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device cap9adk_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &cap9adk_nor_data,
},
.resource = nor_flash_resources,
.num_resources = ARRAY_SIZE(nor_flash_resources),
};
static struct sam9_smc_config __initdata cap9adk_nor_smc_config = {
.ncs_read_setup = 2,
.nrd_setup = 4,
.ncs_write_setup = 2,
.nwe_setup = 4,
.ncs_read_pulse = 10,
.nrd_pulse = 8,
.ncs_write_pulse = 10,
.nwe_pulse = 8,
.read_cycle = 16,
.write_cycle = 16,
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
.tdf_cycles = 1,
};
static __init void cap9adk_add_device_nor(void)
{
unsigned long csa;
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
/* configure chip-select 0 (NOR) */
sam9_smc_configure(0, 0, &cap9adk_nor_smc_config);
platform_device_register(&cap9adk_nor_flash);
}
/*
* LCD Controller
*/
#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
static struct fb_videomode at91_tft_vga_modes[] = {
{
.name = "TX09D50VM1CCA @ 60",
.refresh = 60,
.xres = 240, .yres = 320,
.pixclock = KHZ2PICOS(4965),
.left_margin = 1, .right_margin = 33,
.upper_margin = 1, .lower_margin = 0,
.hsync_len = 5, .vsync_len = 1,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED,
},
};
static struct fb_monspecs at91fb_default_monspecs = {
.manufacturer = "HIT",
.monitor = "TX09D70VM1CCA",
.modedb = at91_tft_vga_modes,
.modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
.hfmin = 15000,
.hfmax = 64000,
.vfmin = 50,
.vfmax = 150,
};
#define AT91CAP9_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
| ATMEL_LCDC_DISTYPE_TFT \
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
static void at91_lcdc_power_control(int on)
{
if (on)
at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
else
at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
}
/* Driver datas */
static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data = {
.default_bpp = 16,
.default_dmacon = ATMEL_LCDC_DMAEN,
.default_lcdcon2 = AT91CAP9_DEFAULT_LCDCON2,
.default_monspecs = &at91fb_default_monspecs,
.atmel_lcdfb_power_control = at91_lcdc_power_control,
.guard_time = 1,
};
#else
static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data;
#endif
/*
* AC97
*/
static struct ac97c_platform_data cap9adk_ac97_data = {
.reset_pin = -EINVAL,
};
static void __init cap9adk_board_init(void)
{
/* Serial */
at91_add_device_serial();
/* USB Host */
at91_add_device_usbh(&cap9adk_usbh_data);
/* USB HS */
at91_add_device_usba(&cap9adk_usba_udc_data);
/* SPI */
at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
/* Touchscreen */
cap9adk_add_device_ts();
/* MMC */
at91_add_device_mmc(1, &cap9adk_mmc_data);
/* Ethernet */
at91_add_device_eth(&cap9adk_macb_data);
/* NAND */
cap9adk_add_device_nand();
/* NOR Flash */
cap9adk_add_device_nor();
/* I2C */
at91_add_device_i2c(NULL, 0);
/* LCD Controller */
at91_add_device_lcdc(&cap9adk_lcdc_data);
/* AC97 */
at91_add_device_ac97(&cap9adk_ac97_data);
}
MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
/* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
.timer = &at91sam926x_timer,
.map_io = at91_map_io,
.init_early = cap9adk_init_early,
.init_irq = at91_init_irq_default,
.init_machine = cap9adk_board_init,
MACHINE_END
arch/arm/mach-at91/board-cpu9krea.c
View file @ 6e1d521b
......@@ -43,6 +43,7 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9260_matrix.h>
#include <mach/at91_matrix.h>
#include "sam9_smc.h"
#include "generic.h"
......@@ -238,8 +239,8 @@ static __init void cpu9krea_add_device_nor(void)
{
unsigned long csa;
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
csa = at91_matrix_read(AT91_MATRIX_EBICSA);
at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
/* configure chip-select 0 (NOR) */
sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
......
arch/arm/mach-at91/board-cpuat91.c
View file @ 6e1d521b
......@@ -38,6 +38,7 @@
#include <mach/board.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include <mach/cpu.h>
#include "generic.h"
......
arch/arm/mach-at91/board-dt.c
View file @ 6e1d521b
......@@ -38,12 +38,6 @@ static void __init ek_init_early(void)
{
/* Initialize processor: 12.000 MHz crystal */
at91_initialize(12000000);
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
/* det_pin is not connected */
......@@ -109,6 +103,7 @@ static void __init at91_dt_device_init(void)
static const char *at91_dt_board_compat[] __initdata = {
"atmel,at91sam9m10g45ek",
"atmel,at91sam9x5ek",
"calao,usb-a9g20",
NULL
};
......
arch/arm/mach-at91/board-eco920.c
View file @ 6e1d521b
......@@ -26,6 +26,7 @@
#include <mach/board.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include <mach/cpu.h>
#include "generic.h"
......@@ -110,7 +111,7 @@ static void __init eco920_board_init(void)
at91_add_device_mmc(0, &eco920_mmc_data);
platform_device_register(&eco920_flash);
at91_sys_write(AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
at91_ramc_write(0, AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
| AT91_SMC_RWSETUP_(1)
| AT91_SMC_DBW_8
| AT91_SMC_WSEN
......@@ -122,7 +123,7 @@ static void __init eco920_board_init(void)
at91_set_deglitch(AT91_PIN_PA23, 1);
/* Initialization of the Static Memory Controller for Chip Select 3 */
at91_sys_write(AT91_SMC_CSR(3),
at91_ramc_write(0, AT91_SMC_CSR(3),
AT91_SMC_DBW_16 | /* 16 bit */
AT91_SMC_WSEN |
AT91_SMC_NWS_(5) | /* wait states */
......
arch/arm/mach-at91/board-flexibity.c
View file @ 6e1d521b
/*
* linux/arch/arm/mach-at91/board-flexibity.c
*
* Copyright (C) 2010 Flexibity
* Copyright (C) 2010-2011 Flexibity
* Copyright (C) 2005 SAN People
* Copyright (C) 2006 Atmel
*
......@@ -62,6 +62,13 @@ static struct at91_udc_data __initdata flexibity_udc_data = {
.pullup_pin = -EINVAL, /* pull-up driven by UDC */
};
/* I2C devices */
static struct i2c_board_info __initdata flexibity_i2c_devices[] = {
{
I2C_BOARD_INFO("ds1307", 0x68),
},
};
/* SPI devices */
static struct spi_board_info flexibity_spi_devices[] = {
{ /* DataFlash chip */
......@@ -141,6 +148,9 @@ static void __init flexibity_board_init(void)
at91_add_device_usbh(&flexibity_usbh_data);
/* USB Device */
at91_add_device_udc(&flexibity_udc_data);
/* I2C */
at91_add_device_i2c(flexibity_i2c_devices,
ARRAY_SIZE(flexibity_i2c_devices));
/* SPI */
at91_add_device_spi(flexibity_spi_devices,
ARRAY_SIZE(flexibity_spi_devices));
......
arch/arm/mach-at91/board-kb9202.c
View file @ 6e1d521b
......@@ -38,6 +38,7 @@
#include <mach/board.h>
#include <mach/cpu.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include "generic.h"
......
arch/arm/mach-at91/board-picotux200.c
View file @ 6e1d521b
......@@ -39,6 +39,7 @@
#include <mach/board.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include "generic.h"
......
arch/arm/mach-at91/board-rm9200dk.c
View file @ 6e1d521b
......@@ -41,6 +41,7 @@
#include <mach/hardware.h>
#include <mach/board.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include "generic.h"
......
arch/arm/mach-at91/board-rm9200ek.c
View file @ 6e1d521b
......@@ -41,6 +41,7 @@
#include <mach/hardware.h>
#include <mach/board.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include "generic.h"
......
arch/arm/mach-at91/board-sam9m10g45ek.c
View file @ 6e1d521b
......@@ -24,11 +24,13 @@
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/leds.h>
#include <linux/clk.h>
#include <linux/atmel-mci.h>
#include <linux/delay.h>
#include <mach/hardware.h>
#include <video/atmel_lcdc.h>
#include <media/soc_camera.h>
#include <media/atmel-isi.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
......@@ -184,6 +186,71 @@ static void __init ek_add_device_nand(void)
}
/*
* ISI
*/
static struct isi_platform_data __initdata isi_data = {
.frate = ISI_CFG1_FRATE_CAPTURE_ALL,
/* to use codec and preview path simultaneously */
.full_mode = 1,
.data_width_flags = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
/* ISI_MCK is provided by programmable clock or external clock */
.mck_hz = 25000000,
};
/*
* soc-camera OV2640
*/
#if defined(CONFIG_SOC_CAMERA_OV2640) || \
defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
{
/* ISI board for ek using default 8-bits connection */
return SOCAM_DATAWIDTH_8;
}
static int i2c_camera_power(struct device *dev, int on)
{
/* enable or disable the camera */
pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
at91_set_gpio_output(AT91_PIN_PD13, !on);
if (!on)
goto out;
/* If enabled, give a reset impulse */
at91_set_gpio_output(AT91_PIN_PD12, 0);
msleep(20);
at91_set_gpio_output(AT91_PIN_PD12, 1);
msleep(100);
out:
return 0;
}
static struct i2c_board_info i2c_camera = {
I2C_BOARD_INFO("ov2640", 0x30),
};
static struct soc_camera_link iclink_ov2640 = {
.bus_id = 0,
.board_info = &i2c_camera,
.i2c_adapter_id = 0,
.power = i2c_camera_power,
.query_bus_param = isi_camera_query_bus_param,
};
static struct platform_device isi_ov2640 = {
.name = "soc-camera-pdrv",
.id = 0,
.dev = {
.platform_data = &iclink_ov2640,
},
};
#endif
/*
* LCD Controller
*/
......@@ -377,7 +444,12 @@ static struct gpio_led ek_pwm_led[] = {
#endif
};
static struct platform_device *devices[] __initdata = {
#if defined(CONFIG_SOC_CAMERA_OV2640) || \
defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
&isi_ov2640,
#endif
};
static void __init ek_board_init(void)
{
......@@ -399,6 +471,8 @@ static void __init ek_board_init(void)
ek_add_device_nand();
/* I2C */
at91_add_device_i2c(0, NULL, 0);
/* ISI, using programmable clock as ISI_MCK */
at91_add_device_isi(&isi_data, true);
/* LCD Controller */
at91_add_device_lcdc(&ek_lcdc_data);
/* Touch Screen */
......@@ -410,6 +484,8 @@ static void __init ek_board_init(void)
/* LEDs */
at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
/* Other platform devices */
platform_add_devices(devices, ARRAY_SIZE(devices));
}
MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
......
arch/arm/mach-at91/board-yl-9200.c
View file @ 6e1d521b
......@@ -45,6 +45,7 @@
#include <mach/hardware.h>
#include <mach/board.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include <mach/cpu.h>
#include "generic.h"
......@@ -393,7 +394,7 @@ static void yl9200_init_video(void)
at91_set_A_periph(AT91_PIN_PC6, 0);
/* Initialization of the Static Memory Controller for Chip Select 2 */
at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
| AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
| AT91_SMC_TDF_(0x100) /* float time */
);
......
arch/arm/mach-at91/clock.c
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arch/arm/mach-at91/cpuidle.c
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......@@ -39,20 +39,15 @@ static int at91_enter_idle(struct cpuidle_device *dev,
{
struct timeval before, after;
int idle_time;
u32 saved_lpr;
local_irq_disable();
do_gettimeofday(&before);
if (index == 0)
/* Wait for interrupt state */
cpu_do_idle();
else if (index == 1) {
asm("b 1f; .align 5; 1:");
asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */
saved_lpr = sdram_selfrefresh_enable();
cpu_do_idle();
sdram_selfrefresh_disable(saved_lpr);
}
else if (index == 1)
at91_standby();
do_gettimeofday(&after);
local_irq_enable();
idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
......
arch/arm/mach-at91/generic.h
View file @ 6e1d521b
......@@ -28,6 +28,7 @@ extern void __init at91_aic_init(unsigned int priority[]);
/* Timer */
struct sys_timer;
extern void at91rm9200_ioremap_st(u32 addr);
extern struct sys_timer at91rm9200_timer;
extern void at91sam926x_ioremap_pit(u32 addr);
extern struct sys_timer at91sam926x_timer;
......@@ -45,7 +46,6 @@ extern void __init at91sam9261_set_console_clock(int id);
extern void __init at91sam9263_set_console_clock(int id);
extern void __init at91sam9rl_set_console_clock(int id);
extern void __init at91sam9g45_set_console_clock(int id);
extern void __init at91cap9_set_console_clock(int id);
#ifdef CONFIG_AT91_PMC_UNIT
extern int __init at91_clock_init(unsigned long main_clock);
#else
......@@ -57,6 +57,9 @@ struct device;
extern void at91_irq_suspend(void);
extern void at91_irq_resume(void);
/* idle */
extern void at91sam9_idle(void);
/* reset */
extern void at91_ioremap_rstc(u32 base_addr);
extern void at91sam9_alt_restart(char, const char *);
......@@ -65,6 +68,12 @@ extern void at91sam9g45_restart(char, const char *);
/* shutdown */
extern void at91_ioremap_shdwc(u32 base_addr);
/* Matrix */
extern void at91_ioremap_matrix(u32 base_addr);
/* Ram Controler */
extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
/* GPIO */
#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
......
arch/arm/mach-at91/include/mach/at91_matrix.h 0 → 100644
View file @ 6e1d521b
/*
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#ifndef __MACH_AT91_MATRIX_H__
#define __MACH_AT91_MATRIX_H__
#ifndef __ASSEMBLY__
extern void __iomem *at91_matrix_base;
#define at91_matrix_read(field) \
__raw_readl(at91_matrix_base + field)
#define at91_matrix_write(field, value) \
__raw_writel(value, at91_matrix_base + field);
#else
.extern at91_matrix_base
#endif
#endif /* __MACH_AT91_MATRIX_H__ */
arch/arm/mach-at91/include/mach/at91_pmc.h
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arch/arm/mach-at91/include/mach/at91_ramc.h 0 → 100644
View file @ 6e1d521b
/*
* Header file for the Atmel RAM Controller
*
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2 only
*/
#ifndef __AT91_RAMC_H__
#define __AT91_RAMC_H__
#ifndef __ASSEMBLY__
extern void __iomem *at91_ramc_base[];
#define at91_ramc_read(id, field) \
__raw_readl(at91_ramc_base[id] + field)
#define at91_ramc_write(id, field, value) \
__raw_writel(value, at91_ramc_base[id] + field)
#else
.extern at91_ramc_base
#endif
#define AT91_MEMCTRL_MC 0
#define AT91_MEMCTRL_SDRAMC 1
#define AT91_MEMCTRL_DDRSDR 2
#include <mach/at91rm9200_sdramc.h>
#include <mach/at91sam9_ddrsdr.h>
#include <mach/at91sam9_sdramc.h>
#endif /* __AT91_RAMC_H__ */
arch/arm/mach-at91/include/mach/at91_st.h
View file @ 6e1d521b
......@@ -16,34 +16,46 @@
#ifndef AT91_ST_H
#define AT91_ST_H
#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
#ifndef __ASSEMBLY__
extern void __iomem *at91_st_base;
#define at91_st_read(field) \
__raw_readl(at91_st_base + field)
#define at91_st_write(field, value) \
__raw_writel(value, at91_st_base + field);
#else
.extern at91_st_base
#endif
#define AT91_ST_CR 0x00 /* Control Register */
#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
#define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */
#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
#define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */
#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
#define AT91_ST_RTMR 0x0c /* Real-time Mode Register */
#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
#define AT91_ST_SR 0x10 /* Status Register */
#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
#define AT91_ST_IER 0x14 /* Interrupt Enable Register */
#define AT91_ST_IDR 0x18 /* Interrupt Disable Register */
#define AT91_ST_IMR 0x1c /* Interrupt Mask Register */
#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
#define AT91_ST_RTAR 0x20 /* Real-time Alarm Register */
#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
#define AT91_ST_CRTR 0x24 /* Current Real-time Register */
#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
#endif
arch/arm/mach-at91/include/mach/at91cap9.h deleted 100644 → 0
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arch/arm/mach-at91/include/mach/at91rm9200.h
View file @ 6e1d521b
......@@ -77,26 +77,22 @@
/*
* System Peripherals (offset from AT91_BASE_SYS)
* System Peripherals
*/
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
#define AT91_USART0 AT91RM9200_BASE_US0
#define AT91_USART1 AT91RM9200_BASE_US1
#define AT91_USART2 AT91RM9200_BASE_US2
#define AT91_USART3 AT91RM9200_BASE_US3
#define AT91_MATRIX 0 /* not supported */
/*
* Internal Memory.
*/
......
arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h 0 → 100644
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arch/arm/mach-at91/include/mach/at91sam9260.h
View file @ 6e1d521b
......@@ -78,15 +78,12 @@
#define AT91SAM9260_BASE_ADC 0xfffe0000
/*
* System Peripherals (offset from AT91_BASE_SYS)
* System Peripherals
*/
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9260_BASE_ECC 0xffffe800
#define AT91SAM9260_BASE_SDRAMC 0xffffea00
#define AT91SAM9260_BASE_SMC 0xffffec00
#define AT91SAM9260_BASE_MATRIX 0xffffee00
#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9260_BASE_PIOA 0xfffff400
#define AT91SAM9260_BASE_PIOB 0xfffff600
......@@ -96,6 +93,7 @@
#define AT91SAM9260_BASE_RTT 0xfffffd20
#define AT91SAM9260_BASE_PIT 0xfffffd30
#define AT91SAM9260_BASE_WDT 0xfffffd40
#define AT91SAM9260_BASE_GPBR 0xfffffd50
#define AT91_USART0 AT91SAM9260_BASE_US0
#define AT91_USART1 AT91SAM9260_BASE_US1
......@@ -115,6 +113,8 @@
#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */
#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */
#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
......@@ -128,6 +128,8 @@
#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */
#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
......
arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
View file @ 6e1d521b
......@@ -82,10 +82,4 @@
#define AT91_SDRAMC_MD_SDRAM 0
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
/* Register access macros */
#define at91_ramc_read(num, reg) \
at91_sys_read(AT91_SDRAMC##num + reg)
#define at91_ramc_write(num, reg, value) \
at91_sys_write(AT91_SDRAMC##num + reg, value)
#endif
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