Commit 6e7a3840 authored by Chunming Zhou's avatar Chunming Zhou Committed by Alex Deucher

drm/amdgpu: use IB for fill_buffer instead of direct command

Signed-off-by: default avatarChunming Zhou <david1.zhou@amd.com>
Reviewed-by: default avatarChristian K?nig <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8f8202f7
...@@ -262,7 +262,7 @@ struct amdgpu_buffer_funcs { ...@@ -262,7 +262,7 @@ struct amdgpu_buffer_funcs {
unsigned fill_num_dw; unsigned fill_num_dw;
/* used for buffer clearing */ /* used for buffer clearing */
void (*emit_fill_buffer)(struct amdgpu_ring *ring, void (*emit_fill_buffer)(struct amdgpu_ib *ib,
/* value to write to memory */ /* value to write to memory */
uint32_t src_data, uint32_t src_data,
/* dst addr in bytes */ /* dst addr in bytes */
...@@ -2248,7 +2248,7 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) ...@@ -2248,7 +2248,7 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
#define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b)) #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
#define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev)) #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
......
...@@ -1363,16 +1363,16 @@ static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib, ...@@ -1363,16 +1363,16 @@ static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
* *
* Fill GPU buffers using the DMA engine (CIK). * Fill GPU buffers using the DMA engine (CIK).
*/ */
static void cik_sdma_emit_fill_buffer(struct amdgpu_ring *ring, static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
uint32_t src_data, uint32_t src_data,
uint64_t dst_offset, uint64_t dst_offset,
uint32_t byte_count) uint32_t byte_count)
{ {
amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0)); ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
amdgpu_ring_write(ring, lower_32_bits(dst_offset)); ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
amdgpu_ring_write(ring, upper_32_bits(dst_offset)); ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
amdgpu_ring_write(ring, src_data); ib->ptr[ib->length_dw++] = src_data;
amdgpu_ring_write(ring, byte_count); ib->ptr[ib->length_dw++] = byte_count;
} }
static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
......
...@@ -1375,16 +1375,16 @@ static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib, ...@@ -1375,16 +1375,16 @@ static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
* *
* Fill GPU buffers using the DMA engine (VI). * Fill GPU buffers using the DMA engine (VI).
*/ */
static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ring *ring, static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
uint32_t src_data, uint32_t src_data,
uint64_t dst_offset, uint64_t dst_offset,
uint32_t byte_count) uint32_t byte_count)
{ {
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)); ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
amdgpu_ring_write(ring, lower_32_bits(dst_offset)); ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
amdgpu_ring_write(ring, upper_32_bits(dst_offset)); ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
amdgpu_ring_write(ring, src_data); ib->ptr[ib->length_dw++] = src_data;
amdgpu_ring_write(ring, byte_count); ib->ptr[ib->length_dw++] = byte_count;
} }
static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
......
...@@ -1499,16 +1499,16 @@ static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, ...@@ -1499,16 +1499,16 @@ static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
* *
* Fill GPU buffers using the DMA engine (VI). * Fill GPU buffers using the DMA engine (VI).
*/ */
static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ring *ring, static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
uint32_t src_data, uint32_t src_data,
uint64_t dst_offset, uint64_t dst_offset,
uint32_t byte_count) uint32_t byte_count)
{ {
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)); ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
amdgpu_ring_write(ring, lower_32_bits(dst_offset)); ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
amdgpu_ring_write(ring, upper_32_bits(dst_offset)); ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
amdgpu_ring_write(ring, src_data); ib->ptr[ib->length_dw++] = src_data;
amdgpu_ring_write(ring, byte_count); ib->ptr[ib->length_dw++] = byte_count;
} }
static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
......
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