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Commit 6e82bdae authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
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perf vendor events: Add SandyBridge V15 event file 

Add a Intel event file for perf.
Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-5x9p0g7q5peodpow01tvayyf@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 1b097845
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tools/perf/pmu-events/arch/x86/mapfile.csv
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......@@ -28,3 +28,4 @@ GenuineIntel-6-9E,v24,skylake,core
GenuineIntel-6-37,v13,silvermont,core
GenuineIntel-6-4D,v13,silvermont,core
GenuineIntel-6-4C,v13,silvermont,core
GenuineIntel-6-2A,v15,sandybridge,core
tools/perf/pmu-events/arch/x86/sandybridge/cache.json 0 → 100644
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tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json 0 → 100644
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[
{
"EventCode": "0xC1",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "OTHER_ASSISTS.AVX_STORE",
"SampleAfterValue": "100003",
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xC1",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue": "100003",
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xC1",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue": "100003",
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "FP_ASSIST.X87_OUTPUT",
"SampleAfterValue": "100003",
"BriefDescription": "Number of X87 assists due to output value.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "FP_ASSIST.X87_INPUT",
"SampleAfterValue": "100003",
"BriefDescription": "Number of X87 assists due to input value.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"SampleAfterValue": "100003",
"BriefDescription": "Number of SIMD FP assists due to Output values.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "FP_ASSIST.SIMD_INPUT",
"SampleAfterValue": "100003",
"BriefDescription": "Number of SIMD FP assists due to input values.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x11",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SIMD_FP_256.PACKED_SINGLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x11",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x1e",
"EventName": "FP_ASSIST.ANY",
"SampleAfterValue": "100003",
"BriefDescription": "Cycles with any input/output SSE or FP assist.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3"
}
]
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tools/perf/pmu-events/arch/x86/sandybridge/frontend.json 0 → 100644
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tools/perf/pmu-events/arch/x86/sandybridge/memory.json 0 → 100644
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tools/perf/pmu-events/arch/x86/sandybridge/other.json 0 → 100644
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[
{
"EventCode": "0x17",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
"SampleAfterValue": "2000003",
"BriefDescription": "Valid instructions written to IQ per cycle.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x5C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CPL_CYCLES.RING0",
"SampleAfterValue": "2000003",
"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x5C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EdgeDetect": "1",
"EventName": "CPL_CYCLES.RING0_TRANS",
"SampleAfterValue": "100007",
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
"CounterMask": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x5C",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "CPL_CYCLES.RING123",
"SampleAfterValue": "2000003",
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x4E",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "HW_PRE_REQ.DL1_MISS",
"SampleAfterValue": "2000003",
"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x63",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json 0 → 100644
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tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json 0 → 100644
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[
{
"EventCode": "0xAE",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB.ITLB_FLUSH",
"SampleAfterValue": "100007",
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x4F",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"BriefDescription": "Misses at all ITLB levels that cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "ITLB_MISSES.WALK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when PMH is busy with page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"BriefDescription": "Load misses in all DTLB levels that cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when PMH is busy with page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses in all DTLB levels that cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles when PMH is busy with page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xBD",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"SampleAfterValue": "100007",
"BriefDescription": "DTLB flush attempts of the thread-specific entries.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xBD",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "TLB_FLUSH.STLB_ANY",
"SampleAfterValue": "100007",
"BriefDescription": "STLB flush attempts.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
}
]
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