Commit 6ee532e2 authored by Linus Walleij's avatar Linus Walleij Committed by Marc Zyngier

irqchip/gemini: Refactor Gemini driver to reflect Faraday origin

The Gemini irqchip turns out to be a standard IP component from
Faraday Technology named FTINTC010 after some research and new
information.

- Rename the driver and all symbols to reflect the new information.
- Add the new compatible string "faraday,ftintc010"
- Create a Kconfig symbol CONFIG_FARADAY_FTINTC010 so that SoCs
  using this interrupt controller can easily select and reuse it
  instead of hardwiring it to ARCH_GEMINI

I have created a separate patch to select the new Kconfig symbol
from the Gemini machine, which will be merged through the ARM
SoC tree.

Cc: Greentime Hu <green.hu@gmail.com>
Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 77a45255
...@@ -115,6 +115,12 @@ config DW_APB_ICTL ...@@ -115,6 +115,12 @@ config DW_APB_ICTL
select GENERIC_IRQ_CHIP select GENERIC_IRQ_CHIP
select IRQ_DOMAIN select IRQ_DOMAIN
config FARADAY_FTINTC010
bool
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
config HISILICON_IRQ_MBIGEN config HISILICON_IRQ_MBIGEN
bool bool
select ARM_GIC_V3 select ARM_GIC_V3
......
...@@ -6,7 +6,7 @@ obj-$(CONFIG_ATH79) += irq-ath79-misc.o ...@@ -6,7 +6,7 @@ obj-$(CONFIG_ATH79) += irq-ath79-misc.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
obj-$(CONFIG_ARCH_GEMINI) += irq-gemini.o obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o
obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o
obj-$(CONFIG_ARCH_MMP) += irq-mmp.o obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
......
/* /*
* irqchip for the Cortina Systems Gemini Copyright (C) 2017 Linus * irqchip for the Faraday Technology FTINTC010 Copyright (C) 2017 Linus
* Walleij <linus.walleij@linaro.org> * Walleij <linus.walleij@linaro.org>
* *
* Based on arch/arm/mach-gemini/irq.c * Based on arch/arm/mach-gemini/irq.c
* Copyright (C) 2001-2006 Storlink, Corp. * Copyright (C) 2001-2006 Storlink, Corp.
* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@gmail.com>
*/ */
#include <linux/bitops.h> #include <linux/bitops.h>
#include <linux/irq.h> #include <linux/irq.h>
...@@ -21,68 +21,68 @@ ...@@ -21,68 +21,68 @@
#include <asm/exception.h> #include <asm/exception.h>
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#define GEMINI_NUM_IRQS 32 #define FT010_NUM_IRQS 32
#define GEMINI_IRQ_SOURCE(base_addr) (base_addr + 0x00) #define FT010_IRQ_SOURCE(base_addr) (base_addr + 0x00)
#define GEMINI_IRQ_MASK(base_addr) (base_addr + 0x04) #define FT010_IRQ_MASK(base_addr) (base_addr + 0x04)
#define GEMINI_IRQ_CLEAR(base_addr) (base_addr + 0x08) #define FT010_IRQ_CLEAR(base_addr) (base_addr + 0x08)
#define GEMINI_IRQ_MODE(base_addr) (base_addr + 0x0C) #define FT010_IRQ_MODE(base_addr) (base_addr + 0x0C)
#define GEMINI_IRQ_POLARITY(base_addr) (base_addr + 0x10) #define FT010_IRQ_POLARITY(base_addr) (base_addr + 0x10)
#define GEMINI_IRQ_STATUS(base_addr) (base_addr + 0x14) #define FT010_IRQ_STATUS(base_addr) (base_addr + 0x14)
#define GEMINI_FIQ_SOURCE(base_addr) (base_addr + 0x20) #define FT010_FIQ_SOURCE(base_addr) (base_addr + 0x20)
#define GEMINI_FIQ_MASK(base_addr) (base_addr + 0x24) #define FT010_FIQ_MASK(base_addr) (base_addr + 0x24)
#define GEMINI_FIQ_CLEAR(base_addr) (base_addr + 0x28) #define FT010_FIQ_CLEAR(base_addr) (base_addr + 0x28)
#define GEMINI_FIQ_MODE(base_addr) (base_addr + 0x2C) #define FT010_FIQ_MODE(base_addr) (base_addr + 0x2C)
#define GEMINI_FIQ_POLARITY(base_addr) (base_addr + 0x30) #define FT010_FIQ_POLARITY(base_addr) (base_addr + 0x30)
#define GEMINI_FIQ_STATUS(base_addr) (base_addr + 0x34) #define FT010_FIQ_STATUS(base_addr) (base_addr + 0x34)
/** /**
* struct gemini_irq_data - irq data container for the Gemini IRQ controller * struct ft010_irq_data - irq data container for the Faraday IRQ controller
* @base: memory offset in virtual memory * @base: memory offset in virtual memory
* @chip: chip container for this instance * @chip: chip container for this instance
* @domain: IRQ domain for this instance * @domain: IRQ domain for this instance
*/ */
struct gemini_irq_data { struct ft010_irq_data {
void __iomem *base; void __iomem *base;
struct irq_chip chip; struct irq_chip chip;
struct irq_domain *domain; struct irq_domain *domain;
}; };
static void gemini_irq_mask(struct irq_data *d) static void ft010_irq_mask(struct irq_data *d)
{ {
struct gemini_irq_data *g = irq_data_get_irq_chip_data(d); struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
unsigned int mask; unsigned int mask;
mask = readl(GEMINI_IRQ_MASK(g->base)); mask = readl(FT010_IRQ_MASK(f->base));
mask &= ~BIT(irqd_to_hwirq(d)); mask &= ~BIT(irqd_to_hwirq(d));
writel(mask, GEMINI_IRQ_MASK(g->base)); writel(mask, FT010_IRQ_MASK(f->base));
} }
static void gemini_irq_unmask(struct irq_data *d) static void ft010_irq_unmask(struct irq_data *d)
{ {
struct gemini_irq_data *g = irq_data_get_irq_chip_data(d); struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
unsigned int mask; unsigned int mask;
mask = readl(GEMINI_IRQ_MASK(g->base)); mask = readl(FT010_IRQ_MASK(f->base));
mask |= BIT(irqd_to_hwirq(d)); mask |= BIT(irqd_to_hwirq(d));
writel(mask, GEMINI_IRQ_MASK(g->base)); writel(mask, FT010_IRQ_MASK(f->base));
} }
static void gemini_irq_ack(struct irq_data *d) static void ft010_irq_ack(struct irq_data *d)
{ {
struct gemini_irq_data *g = irq_data_get_irq_chip_data(d); struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
writel(BIT(irqd_to_hwirq(d)), GEMINI_IRQ_CLEAR(g->base)); writel(BIT(irqd_to_hwirq(d)), FT010_IRQ_CLEAR(f->base));
} }
static int gemini_irq_set_type(struct irq_data *d, unsigned int trigger) static int ft010_irq_set_type(struct irq_data *d, unsigned int trigger)
{ {
struct gemini_irq_data *g = irq_data_get_irq_chip_data(d); struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
int offset = irqd_to_hwirq(d); int offset = irqd_to_hwirq(d);
u32 mode, polarity; u32 mode, polarity;
mode = readl(GEMINI_IRQ_MODE(g->base)); mode = readl(FT010_IRQ_MODE(f->base));
polarity = readl(GEMINI_IRQ_POLARITY(g->base)); polarity = readl(FT010_IRQ_POLARITY(f->base));
if (trigger & (IRQ_TYPE_LEVEL_HIGH)) { if (trigger & (IRQ_TYPE_LEVEL_HIGH)) {
irq_set_handler_locked(d, handle_level_irq); irq_set_handler_locked(d, handle_level_irq);
...@@ -103,64 +103,64 @@ static int gemini_irq_set_type(struct irq_data *d, unsigned int trigger) ...@@ -103,64 +103,64 @@ static int gemini_irq_set_type(struct irq_data *d, unsigned int trigger)
offset); offset);
} }
writel(mode, GEMINI_IRQ_MODE(g->base)); writel(mode, FT010_IRQ_MODE(f->base));
writel(polarity, GEMINI_IRQ_POLARITY(g->base)); writel(polarity, FT010_IRQ_POLARITY(f->base));
return 0; return 0;
} }
static struct irq_chip gemini_irq_chip = { static struct irq_chip ft010_irq_chip = {
.name = "GEMINI", .name = "FTINTC010",
.irq_ack = gemini_irq_ack, .irq_ack = ft010_irq_ack,
.irq_mask = gemini_irq_mask, .irq_mask = ft010_irq_mask,
.irq_unmask = gemini_irq_unmask, .irq_unmask = ft010_irq_unmask,
.irq_set_type = gemini_irq_set_type, .irq_set_type = ft010_irq_set_type,
}; };
/* Local static for the IRQ entry call */ /* Local static for the IRQ entry call */
static struct gemini_irq_data girq; static struct ft010_irq_data firq;
asmlinkage void __exception_irq_entry gemini_irqchip_handle_irq(struct pt_regs *regs) asmlinkage void __exception_irq_entry ft010_irqchip_handle_irq(struct pt_regs *regs)
{ {
struct gemini_irq_data *g = &girq; struct ft010_irq_data *f = &firq;
int irq; int irq;
u32 status; u32 status;
while ((status = readl(GEMINI_IRQ_STATUS(g->base)))) { while ((status = readl(FT010_IRQ_STATUS(f->base)))) {
irq = ffs(status) - 1; irq = ffs(status) - 1;
handle_domain_irq(g->domain, irq, regs); handle_domain_irq(f->domain, irq, regs);
} }
} }
static int gemini_irqdomain_map(struct irq_domain *d, unsigned int irq, static int ft010_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq) irq_hw_number_t hwirq)
{ {
struct gemini_irq_data *g = d->host_data; struct ft010_irq_data *f = d->host_data;
irq_set_chip_data(irq, g); irq_set_chip_data(irq, f);
/* All IRQs should set up their type, flags as bad by default */ /* All IRQs should set up their type, flags as bad by default */
irq_set_chip_and_handler(irq, &gemini_irq_chip, handle_bad_irq); irq_set_chip_and_handler(irq, &ft010_irq_chip, handle_bad_irq);
irq_set_probe(irq); irq_set_probe(irq);
return 0; return 0;
} }
static void gemini_irqdomain_unmap(struct irq_domain *d, unsigned int irq) static void ft010_irqdomain_unmap(struct irq_domain *d, unsigned int irq)
{ {
irq_set_chip_and_handler(irq, NULL, NULL); irq_set_chip_and_handler(irq, NULL, NULL);
irq_set_chip_data(irq, NULL); irq_set_chip_data(irq, NULL);
} }
static const struct irq_domain_ops gemini_irqdomain_ops = { static const struct irq_domain_ops ft010_irqdomain_ops = {
.map = gemini_irqdomain_map, .map = ft010_irqdomain_map,
.unmap = gemini_irqdomain_unmap, .unmap = ft010_irqdomain_unmap,
.xlate = irq_domain_xlate_onetwocell, .xlate = irq_domain_xlate_onetwocell,
}; };
int __init gemini_of_init_irq(struct device_node *node, int __init ft010_of_init_irq(struct device_node *node,
struct device_node *parent) struct device_node *parent)
{ {
struct gemini_irq_data *g = &girq; struct ft010_irq_data *f = &firq;
/* /*
* Disable the idle handler by default since it is buggy * Disable the idle handler by default since it is buggy
...@@ -168,18 +168,20 @@ int __init gemini_of_init_irq(struct device_node *node, ...@@ -168,18 +168,20 @@ int __init gemini_of_init_irq(struct device_node *node,
*/ */
cpu_idle_poll_ctrl(true); cpu_idle_poll_ctrl(true);
g->base = of_iomap(node, 0); f->base = of_iomap(node, 0);
WARN(!g->base, "unable to map gemini irq registers\n"); WARN(!f->base, "unable to map gemini irq registers\n");
/* Disable all interrupts */ /* Disable all interrupts */
writel(0, GEMINI_IRQ_MASK(g->base)); writel(0, FT010_IRQ_MASK(f->base));
writel(0, GEMINI_FIQ_MASK(g->base)); writel(0, FT010_FIQ_MASK(f->base));
g->domain = irq_domain_add_simple(node, GEMINI_NUM_IRQS, 0, f->domain = irq_domain_add_simple(node, FT010_NUM_IRQS, 0,
&gemini_irqdomain_ops, g); &ft010_irqdomain_ops, f);
set_handle_irq(gemini_irqchip_handle_irq); set_handle_irq(ft010_irqchip_handle_irq);
return 0; return 0;
} }
IRQCHIP_DECLARE(faraday, "faraday,ftintc010",
ft010_of_init_irq);
IRQCHIP_DECLARE(gemini, "cortina,gemini-interrupt-controller", IRQCHIP_DECLARE(gemini, "cortina,gemini-interrupt-controller",
gemini_of_init_irq); ft010_of_init_irq);
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