Commit 6f15c506 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie

drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices

If the ss clock is external, the CLK_REF bit needs to be set
in the SetPixelClock parameters.  This should fix DP failures
in the channel equalization loop.
Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@gmail.com>
parent d291767b
...@@ -815,6 +815,8 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc, ...@@ -815,6 +815,8 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
args.v3.ucPostDiv = post_div; args.v3.ucPostDiv = post_div;
args.v3.ucPpll = pll_id; args.v3.ucPpll = pll_id;
args.v3.ucMiscInfo = (pll_id << 2); args.v3.ucMiscInfo = (pll_id << 2);
if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
args.v3.ucTransmitterId = encoder_id; args.v3.ucTransmitterId = encoder_id;
args.v3.ucEncoderMode = encoder_mode; args.v3.ucEncoderMode = encoder_mode;
break; break;
......
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