Commit 70421257 authored by Marcus Cooper's avatar Marcus Cooper Committed by Maxime Ripard

clk: sunxi-ng: A31: Fix spdif clock register

As the SPDIF was rarely documented on the earlier Allwinner SoCs
it was assumed that it had a similar clock register to the one
described in the H3 User Manual.

However this is not the case and it looks to shares the same setup
as the I2S clock registers.
Signed-off-by: default avatarMarcus Cooper <codekipper@gmail.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent bb021cda
...@@ -468,8 +468,8 @@ static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents, ...@@ -468,8 +468,8 @@ static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents,
static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents, static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents,
0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", daudio_parents,
0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(8), 0); 0x0cc, BIT(8), 0);
......
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