Commit 707d33cb authored by Jiancheng Xue's avatar Jiancheng Xue Committed by Stephen Boyd

clk: hisilicon: add CRG driver for Hi3798CV200 SoC

Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.
Signed-off-by: default avatarJiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 1001354c
* Hisilicon Hi3519 Clock and Reset Generator(CRG) * HiSilicon Clock and Reset Generator(CRG)
The Hi3519 CRG module provides clock and reset signals to various The CRG module provides clock and reset signals to various
controllers within the SoC. modules within the SoC.
This binding uses the following bindings: This binding uses the following bindings:
Documentation/devicetree/bindings/clock/clock-bindings.txt Documentation/devicetree/bindings/clock/clock-bindings.txt
...@@ -10,7 +10,11 @@ This binding uses the following bindings: ...@@ -10,7 +10,11 @@ This binding uses the following bindings:
Required Properties: Required Properties:
- compatible: should be one of the following. - compatible: should be one of the following.
- "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC. - "hisilicon,hi3516cv300-crg"
- "hisilicon,hi3516cv300-sysctrl"
- "hisilicon,hi3519-crg"
- "hisilicon,hi3798cv200-crg"
- "hisilicon,hi3798cv200-sysctrl"
- reg: physical base address of the controller and length of memory mapped - reg: physical base address of the controller and length of memory mapped
region. region.
......
...@@ -6,6 +6,14 @@ config COMMON_CLK_HI3519 ...@@ -6,6 +6,14 @@ config COMMON_CLK_HI3519
help help
Build the clock driver for hi3519. Build the clock driver for hi3519.
config COMMON_CLK_HI3798CV200
tristate "Hi3798CV200 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
select RESET_HISI
default ARCH_HISI
help
Build the clock driver for hi3798cv200.
config COMMON_CLK_HI6220 config COMMON_CLK_HI6220
bool "Hi6220 Clock Driver" bool "Hi6220 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST depends on ARCH_HISI || COMPILE_TEST
......
...@@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o ...@@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
obj-$(CONFIG_RESET_HISI) += reset.o obj-$(CONFIG_RESET_HISI) += reset.o
obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
This diff is collapsed.
/*
* HiSilicon Clock and Reset Driver Header
*
* Copyright (c) 2016 HiSilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __HISI_CRG_H
#define __HISI_CRG_H
struct hisi_clock_data;
struct hisi_reset_controller;
struct hisi_crg_funcs {
struct hisi_clock_data* (*register_clks)(struct platform_device *pdev);
void (*unregister_clks)(struct platform_device *pdev);
};
struct hisi_crg_dev {
struct hisi_clock_data *clk_data;
struct hisi_reset_controller *rstc;
const struct hisi_crg_funcs *funcs;
};
#endif /* __HISI_CRG_H */
/*
* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __DTS_HISTB_CLOCK_H
#define __DTS_HISTB_CLOCK_H
/* clocks provided by core CRG */
#define HISTB_OSC_CLK 0
#define HISTB_APB_CLK 1
#define HISTB_AHB_CLK 2
#define HISTB_UART1_CLK 3
#define HISTB_UART2_CLK 4
#define HISTB_UART3_CLK 5
#define HISTB_I2C0_CLK 6
#define HISTB_I2C1_CLK 7
#define HISTB_I2C2_CLK 8
#define HISTB_I2C3_CLK 9
#define HISTB_I2C4_CLK 10
#define HISTB_I2C5_CLK 11
#define HISTB_SPI0_CLK 12
#define HISTB_SPI1_CLK 13
#define HISTB_SPI2_CLK 14
#define HISTB_SCI_CLK 15
#define HISTB_FMC_CLK 16
#define HISTB_MMC_BIU_CLK 17
#define HISTB_MMC_CIU_CLK 18
#define HISTB_MMC_DRV_CLK 19
#define HISTB_MMC_SAMPLE_CLK 20
#define HISTB_SDIO0_BIU_CLK 21
#define HISTB_SDIO0_CIU_CLK 22
#define HISTB_SDIO0_DRV_CLK 23
#define HISTB_SDIO0_SAMPLE_CLK 24
#define HISTB_PCIE_AUX_CLK 25
#define HISTB_PCIE_PIPE_CLK 26
#define HISTB_PCIE_SYS_CLK 27
#define HISTB_PCIE_BUS_CLK 28
#define HISTB_ETH0_MAC_CLK 29
#define HISTB_ETH0_MACIF_CLK 30
#define HISTB_ETH1_MAC_CLK 31
#define HISTB_ETH1_MACIF_CLK 32
#define HISTB_COMBPHY1_CLK 33
/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1
#define HISTB_IR_CLK 2
#define HISTB_TIMER01_CLK 3
#define HISTB_LEDC_CLK 4
#define HISTB_UART0_CLK 5
#define HISTB_LSADC_CLK 6
#endif /* __DTS_HISTB_CLOCK_H */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment