Commit 70c01f01 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6

* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6:
  [IA64] Don't go beyond iosapic_intr_info's arraysize
  [IA64] Do not go beyond ARRAY_SIZE of unw.hash
  [IA64] enable setting DMAR on by default
parents c4eb1bf6 5b592397
...@@ -638,6 +638,17 @@ config DMAR ...@@ -638,6 +638,17 @@ config DMAR
and include PCI device scope covered by these DMA and include PCI device scope covered by these DMA
remapping devices. remapping devices.
config DMAR_DEFAULT_ON
def_bool y
prompt "Enable DMA Remapping Devices by default"
depends on DMAR
help
Selecting this option will enable a DMAR device at boot time if
one is found. If this option is not selected, DMAR support can
be enabled by passing intel_iommu=on to the kernel. It is
recommended you say N here while the DMAR code remains
experimental.
endmenu endmenu
endif endif
......
...@@ -507,7 +507,7 @@ static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol) ...@@ -507,7 +507,7 @@ static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol)
if (trigger == IOSAPIC_EDGE) if (trigger == IOSAPIC_EDGE)
return -EINVAL; return -EINVAL;
for (i = 0; i <= NR_IRQS; i++) { for (i = 0; i < NR_IRQS; i++) {
info = &iosapic_intr_info[i]; info = &iosapic_intr_info[i];
if (info->trigger == trigger && info->polarity == pol && if (info->trigger == trigger && info->polarity == pol &&
(info->dmode == IOSAPIC_FIXED || (info->dmode == IOSAPIC_FIXED ||
......
...@@ -2149,7 +2149,7 @@ unw_remove_unwind_table (void *handle) ...@@ -2149,7 +2149,7 @@ unw_remove_unwind_table (void *handle)
/* next, remove hash table entries for this table */ /* next, remove hash table entries for this table */
for (index = 0; index <= UNW_HASH_SIZE; ++index) { for (index = 0; index < UNW_HASH_SIZE; ++index) {
tmp = unw.cache + unw.hash[index]; tmp = unw.cache + unw.hash[index];
if (unw.hash[index] >= UNW_CACHE_SIZE if (unw.hash[index] >= UNW_CACHE_SIZE
|| tmp->ip < table->start || tmp->ip >= table->end) || tmp->ip < table->start || tmp->ip >= table->end)
......
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