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Commit 70f767d3 authored by David S. Miller's avatar David S. Miller
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Merge branch '10GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 

Jeff Kirsher says:

====================
10GbE Intel Wired LAN Driver Updates 2016-04-07

This series contains updates to ixgbe and ixgbevf.

This entire series (except for one patch from Alex) comes from Mark and
is mainly to add support for our new MAC (x550em_a).

So let's get Alex's patch out of the way first before we cover Mark's
many changes.  Alex does his enable bulk free in transmit cleanup for
ixgbe and ixgbevf, like his has done for all of our other drivers.

First Mark cleans up registers that were not being used, so do some
house cleaning.  Then to avoid casting lan_id and func fields, just
make them u8 since they only hold small values anyways.  Found and
fixed an issue where on read operations it could be possible to
modify locations beyond the length passed in, so change the check
to round up in the same way.  Cleaned up the interface for issuing
firmware commands to use a void * instead of a u32 * which eliminates
a number of casts.  Added support for the new MAC and provided method
pointers and use them to access IOSF-attached devices, since the
new MAC will also need a new access method.  Added support for SFPs
with an external retimer and for an SGMII backplane interface.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents f8711655 10ef00fe
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Inline Side-by-side
Showing with 786 additions and 106 deletions
drivers/net/ethernet/intel/ixgbe/ixgbe.h
View file @ 70f767d3
...@@ -817,6 +817,7 @@ static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) ...@@ -817,6 +817,7 @@ static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter)
return IXGBE_MAX_RSS_INDICES; return IXGBE_MAX_RSS_INDICES;
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
return IXGBE_MAX_RSS_INDICES_X550; return IXGBE_MAX_RSS_INDICES_X550;
default: default:
return 0; return 0;
...@@ -860,6 +861,7 @@ enum ixgbe_boards { ...@@ -860,6 +861,7 @@ enum ixgbe_boards {
board_X540, board_X540,
board_X550, board_X550,
board_X550EM_x, board_X550EM_x,
board_x550em_a,
}; };
extern const struct ixgbe_info ixgbe_82598_info; extern const struct ixgbe_info ixgbe_82598_info;
...@@ -867,6 +869,7 @@ extern const struct ixgbe_info ixgbe_82599_info; ...@@ -867,6 +869,7 @@ extern const struct ixgbe_info ixgbe_82599_info;
extern const struct ixgbe_info ixgbe_X540_info; extern const struct ixgbe_info ixgbe_X540_info;
extern const struct ixgbe_info ixgbe_X550_info; extern const struct ixgbe_info ixgbe_X550_info;
extern const struct ixgbe_info ixgbe_X550EM_x_info; extern const struct ixgbe_info ixgbe_X550EM_x_info;
extern const struct ixgbe_info ixgbe_x550em_a_info;
#ifdef CONFIG_IXGBE_DCB #ifdef CONFIG_IXGBE_DCB
extern const struct dcbnl_rtnl_ops dcbnl_ops; extern const struct dcbnl_rtnl_ops dcbnl_ops;
#endif #endif
......
drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
View file @ 70f767d3
...@@ -1633,6 +1633,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, ...@@ -1633,6 +1633,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
switch (hw->mac.type) { switch (hw->mac.type) {
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
break; break;
default: default:
......
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
View file @ 70f767d3
...@@ -97,6 +97,7 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) ...@@ -97,6 +97,7 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
case IXGBE_DEV_ID_X540T: case IXGBE_DEV_ID_X540T:
case IXGBE_DEV_ID_X540T1: case IXGBE_DEV_ID_X540T1:
case IXGBE_DEV_ID_X550T: case IXGBE_DEV_ID_X550T:
case IXGBE_DEV_ID_X550T1:
case IXGBE_DEV_ID_X550EM_X_10G_T: case IXGBE_DEV_ID_X550EM_X_10G_T:
supported = true; supported = true;
break; break;
...@@ -681,6 +682,7 @@ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) ...@@ -681,6 +682,7 @@ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
{ {
struct ixgbe_bus_info *bus = &hw->bus; struct ixgbe_bus_info *bus = &hw->bus;
u16 ee_ctrl_4;
u32 reg; u32 reg;
reg = IXGBE_READ_REG(hw, IXGBE_STATUS); reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
...@@ -691,6 +693,13 @@ void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) ...@@ -691,6 +693,13 @@ void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));
if (reg & IXGBE_FACTPS_LFS) if (reg & IXGBE_FACTPS_LFS)
bus->func ^= 0x1; bus->func ^= 0x1;
/* Get MAC instance from EEPROM for configuring CS4227 */
if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
IXGBE_EE_CTRL_4_INST_ID_SHIFT;
}
} }
/** /**
...@@ -2854,6 +2863,7 @@ u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) ...@@ -2854,6 +2863,7 @@ u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
break; break;
...@@ -3483,18 +3493,27 @@ static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) ...@@ -3483,18 +3493,27 @@ static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
* Communicates with the manageability block. On success return 0 * Communicates with the manageability block. On success return 0
* else return IXGBE_ERR_HOST_INTERFACE_COMMAND. * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
**/ **/
s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer,
u32 length, u32 timeout, u32 length, u32 timeout,
bool return_data) bool return_data)
{ {
u32 hicr, i, bi, fwsts;
u32 hdr_size = sizeof(struct ixgbe_hic_hdr); u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
u32 hicr, i, bi, fwsts;
u16 buf_len, dword_len; u16 buf_len, dword_len;
union {
struct ixgbe_hic_hdr hdr;
u32 u32arr[1];
} *bp = buffer;
s32 status;
if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
return IXGBE_ERR_HOST_INTERFACE_COMMAND; return IXGBE_ERR_HOST_INTERFACE_COMMAND;
} }
/* Take management host interface semaphore */
status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
if (status)
return status;
/* Set bit 9 of FWSTS clearing FW reset indication */ /* Set bit 9 of FWSTS clearing FW reset indication */
fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
...@@ -3502,26 +3521,27 @@ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, ...@@ -3502,26 +3521,27 @@ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
/* Check that the host interface is enabled. */ /* Check that the host interface is enabled. */
hicr = IXGBE_READ_REG(hw, IXGBE_HICR); hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
if ((hicr & IXGBE_HICR_EN) == 0) { if (!(hicr & IXGBE_HICR_EN)) {
hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
return IXGBE_ERR_HOST_INTERFACE_COMMAND; status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
goto rel_out;
} }
/* Calculate length in DWORDs. We must be DWORD aligned */ /* Calculate length in DWORDs. We must be DWORD aligned */
if ((length % (sizeof(u32))) != 0) { if (length % sizeof(u32)) {
hw_dbg(hw, "Buffer length failure, not aligned to dword"); hw_dbg(hw, "Buffer length failure, not aligned to dword");
return IXGBE_ERR_INVALID_ARGUMENT; status = IXGBE_ERR_INVALID_ARGUMENT;
goto rel_out;
} }
dword_len = length >> 2; dword_len = length >> 2;
/* /* The device driver writes the relevant command block
* The device driver writes the relevant command block
* into the ram area. * into the ram area.
*/ */
for (i = 0; i < dword_len; i++) for (i = 0; i < dword_len; i++)
IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
i, cpu_to_le32(buffer[i])); i, cpu_to_le32(bp->u32arr[i]));
/* Setting this bit tells the ARC that a new command is pending. */ /* Setting this bit tells the ARC that a new command is pending. */
IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
...@@ -3534,44 +3554,49 @@ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, ...@@ -3534,44 +3554,49 @@ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
} }
/* Check command successful completion. */ /* Check command successful completion. */
if ((timeout != 0 && i == timeout) || if ((timeout && i == timeout) ||
(!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) { !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
hw_dbg(hw, "Command has failed with no status valid.\n"); hw_dbg(hw, "Command has failed with no status valid.\n");
return IXGBE_ERR_HOST_INTERFACE_COMMAND; status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
goto rel_out;
} }
if (!return_data) if (!return_data)
return 0; goto rel_out;
/* Calculate length in DWORDs */ /* Calculate length in DWORDs */
dword_len = hdr_size >> 2; dword_len = hdr_size >> 2;
/* first pull in the header so we know the buffer length */ /* first pull in the header so we know the buffer length */
for (bi = 0; bi < dword_len; bi++) { for (bi = 0; bi < dword_len; bi++) {
buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
le32_to_cpus(&buffer[bi]); le32_to_cpus(&bp->u32arr[bi]);
} }
/* If there is any thing in data position pull it in */ /* If there is any thing in data position pull it in */
buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len; buf_len = bp->hdr.buf_len;
if (buf_len == 0) if (!buf_len)
return 0; goto rel_out;
if (length < (buf_len + hdr_size)) { if (length < round_up(buf_len, 4) + hdr_size) {
hw_dbg(hw, "Buffer not large enough for reply message.\n"); hw_dbg(hw, "Buffer not large enough for reply message.\n");
return IXGBE_ERR_HOST_INTERFACE_COMMAND; status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
goto rel_out;
} }
/* Calculate length in DWORDs, add 3 for odd lengths */ /* Calculate length in DWORDs, add 3 for odd lengths */
dword_len = (buf_len + 3) >> 2; dword_len = (buf_len + 3) >> 2;
/* Pull in the rest of the buffer (bi is where we left off)*/ /* Pull in the rest of the buffer (bi is where we left off) */
for (; bi <= dword_len; bi++) { for (; bi <= dword_len; bi++) {
buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
le32_to_cpus(&buffer[bi]); le32_to_cpus(&bp->u32arr[bi]);
} }
return 0; rel_out:
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
return status;
} }
/** /**
...@@ -3594,13 +3619,10 @@ s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, ...@@ -3594,13 +3619,10 @@ s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
int i; int i;
s32 ret_val; s32 ret_val;
if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM))
return IXGBE_ERR_SWFW_SYNC;
fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
fw_cmd.port_num = (u8)hw->bus.func; fw_cmd.port_num = hw->bus.func;
fw_cmd.ver_maj = maj; fw_cmd.ver_maj = maj;
fw_cmd.ver_min = min; fw_cmd.ver_min = min;
fw_cmd.ver_build = build; fw_cmd.ver_build = build;
...@@ -3612,7 +3634,7 @@ s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, ...@@ -3612,7 +3634,7 @@ s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
fw_cmd.pad2 = 0; fw_cmd.pad2 = 0;
for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, ret_val = ixgbe_host_interface_command(hw, &fw_cmd,
sizeof(fw_cmd), sizeof(fw_cmd),
IXGBE_HI_COMMAND_TIMEOUT, IXGBE_HI_COMMAND_TIMEOUT,
true); true);
...@@ -3628,7 +3650,6 @@ s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, ...@@ -3628,7 +3650,6 @@ s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
break; break;
} }
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
return ret_val; return ret_val;
} }
......
drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
View file @ 70f767d3
...@@ -111,8 +111,8 @@ void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf); ...@@ -111,8 +111,8 @@ void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps); s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
u8 build, u8 ver); u8 build, u8 ver);
s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *, u32 length,
u32 length, u32 timeout, bool return_data); u32 timeout, bool return_data);
void ixgbe_clear_tx_pending(struct ixgbe_hw *hw); void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
bool ixgbe_mng_present(struct ixgbe_hw *hw); bool ixgbe_mng_present(struct ixgbe_hw *hw);
bool ixgbe_mng_enabled(struct ixgbe_hw *hw); bool ixgbe_mng_enabled(struct ixgbe_hw *hw);
......
drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c
View file @ 70f767d3
/******************************************************************************* /*******************************************************************************
Intel 10 Gigabit PCI Express Linux driver Intel 10 Gigabit PCI Express Linux driver
Copyright(c) 1999 - 2014 Intel Corporation. Copyright(c) 1999 - 2016 Intel Corporation.
This program is free software; you can redistribute it and/or modify it This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License, under the terms and conditions of the GNU General Public License,
...@@ -293,6 +293,7 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, ...@@ -293,6 +293,7 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
return ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max, return ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max,
bwgid, ptype, prio_tc); bwgid, ptype, prio_tc);
default: default:
...@@ -311,6 +312,7 @@ s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) ...@@ -311,6 +312,7 @@ s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
return ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc); return ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
default: default:
break; break;
...@@ -368,6 +370,7 @@ s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, ...@@ -368,6 +370,7 @@ s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max,
bwg_id, prio_type, prio_tc); bwg_id, prio_type, prio_tc);
ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
...@@ -398,6 +401,7 @@ void ixgbe_dcb_read_rtrup2tc(struct ixgbe_hw *hw, u8 *map) ...@@ -398,6 +401,7 @@ void ixgbe_dcb_read_rtrup2tc(struct ixgbe_hw *hw, u8 *map)
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
ixgbe_dcb_read_rtrup2tc_82599(hw, map); ixgbe_dcb_read_rtrup2tc_82599(hw, map);
break; break;
default: default:
......
drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
View file @ 70f767d3
/******************************************************************************* /*******************************************************************************
Intel 10 Gigabit PCI Express Linux driver Intel 10 Gigabit PCI Express Linux driver
Copyright(c) 1999 - 2014 Intel Corporation. Copyright(c) 1999 - 2016 Intel Corporation.
This program is free software; you can redistribute it and/or modify it This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License, under the terms and conditions of the GNU General Public License,
...@@ -547,6 +547,7 @@ static void ixgbe_get_regs(struct net_device *netdev, ...@@ -547,6 +547,7 @@ static void ixgbe_get_regs(struct net_device *netdev,
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
break; break;
...@@ -660,6 +661,7 @@ static void ixgbe_get_regs(struct net_device *netdev, ...@@ -660,6 +661,7 @@ static void ixgbe_get_regs(struct net_device *netdev,
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS); regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS); regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
for (i = 0; i < 8; i++) for (i = 0; i < 8; i++)
...@@ -1443,6 +1445,7 @@ static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) ...@@ -1443,6 +1445,7 @@ static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
toggle = 0x7FFFF30F; toggle = 0x7FFFF30F;
test = reg_test_82599; test = reg_test_82599;
break; break;
...@@ -1681,6 +1684,7 @@ static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) ...@@ -1681,6 +1684,7 @@ static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
reg_ctl &= ~IXGBE_DMATXCTL_TE; reg_ctl &= ~IXGBE_DMATXCTL_TE;
IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
...@@ -1720,6 +1724,7 @@ static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) ...@@ -1720,6 +1724,7 @@ static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
reg_data |= IXGBE_DMATXCTL_TE; reg_data |= IXGBE_DMATXCTL_TE;
IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
...@@ -1780,6 +1785,7 @@ static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) ...@@ -1780,6 +1785,7 @@ static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
reg_data |= IXGBE_MACC_FLU; reg_data |= IXGBE_MACC_FLU;
IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
...@@ -2991,6 +2997,7 @@ static int ixgbe_get_ts_info(struct net_device *dev, ...@@ -2991,6 +2997,7 @@ static int ixgbe_get_ts_info(struct net_device *dev,
switch (adapter->hw.mac.type) { switch (adapter->hw.mac.type) {
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_82599EB: case ixgbe_mac_82599EB:
info->so_timestamping = info->so_timestamping =
......
drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
View file @ 70f767d3
/******************************************************************************* /*******************************************************************************
Intel 10 Gigabit PCI Express Linux driver Intel 10 Gigabit PCI Express Linux driver
Copyright(c) 1999 - 2013 Intel Corporation. Copyright(c) 1999 - 2016 Intel Corporation.
This program is free software; you can redistribute it and/or modify it This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License, under the terms and conditions of the GNU General Public License,
...@@ -128,6 +128,7 @@ static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc, ...@@ -128,6 +128,7 @@ static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
if (num_tcs > 4) { if (num_tcs > 4) {
/* /*
* TCs : TC0/1 TC2/3 TC4-7 * TCs : TC0/1 TC2/3 TC4-7
......
drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c
View file @ 70f767d3
...@@ -307,6 +307,7 @@ static s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number) ...@@ -307,6 +307,7 @@ static s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number)
case ixgbe_mac_X540: case ixgbe_mac_X540:
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset)); vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));
break; break;
default: default:
...@@ -430,6 +431,7 @@ void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw) ...@@ -430,6 +431,7 @@ void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw)
if (hw->mac.type != ixgbe_mac_82599EB && if (hw->mac.type != ixgbe_mac_82599EB &&
hw->mac.type != ixgbe_mac_X550 && hw->mac.type != ixgbe_mac_X550 &&
hw->mac.type != ixgbe_mac_X550EM_x && hw->mac.type != ixgbe_mac_X550EM_x &&
hw->mac.type != ixgbe_mac_x550em_a &&
hw->mac.type != ixgbe_mac_X540) hw->mac.type != ixgbe_mac_X540)
return; return;
......
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
View file @ 70f767d3
/******************************************************************************* /*******************************************************************************
Intel 10 Gigabit PCI Express Linux driver Intel 10 Gigabit PCI Express Linux driver
Copyright(c) 1999 - 2014 Intel Corporation. Copyright(c) 1999 - 2016 Intel Corporation.
This program is free software; you can redistribute it and/or modify it This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License, under the terms and conditions of the GNU General Public License,
...@@ -81,7 +81,11 @@ ...@@ -81,7 +81,11 @@
#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
#define IXGBE_CS4227 0xBE /* CS4227 address */ #define IXGBE_CS4227 0xBE /* CS4227 address */
#define IXGBE_CS4227_GLOBAL_ID_LSB 0
#define IXGBE_CS4227_GLOBAL_ID_MSB 1
#define IXGBE_CS4227_SCRATCH 2 #define IXGBE_CS4227_SCRATCH 2
#define IXGBE_CS4223_PHY_ID 0x7003 /* Quad port */
#define IXGBE_CS4227_PHY_ID 0x3003 /* Dual port */
#define IXGBE_CS4227_RESET_PENDING 0x1357 #define IXGBE_CS4227_RESET_PENDING 0x1357
#define IXGBE_CS4227_RESET_COMPLETE 0x5AA5 #define IXGBE_CS4227_RESET_COMPLETE 0x5AA5
#define IXGBE_CS4227_RETRIES 15 #define IXGBE_CS4227_RETRIES 15
......
drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
View file @ 70f767d3
/******************************************************************************* /*******************************************************************************
Intel 10 Gigabit PCI Express Linux driver Intel 10 Gigabit PCI Express Linux driver
Copyright(c) 1999 - 2015 Intel Corporation. Copyright(c) 1999 - 2016 Intel Corporation.
This program is free software; you can redistribute it and/or modify it This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License, under the terms and conditions of the GNU General Public License,
...@@ -333,6 +333,7 @@ static void ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter *adapter, ...@@ -333,6 +333,7 @@ static void ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter *adapter,
*/ */
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
/* Upper 32 bits represent billions of cycles, lower 32 bits /* Upper 32 bits represent billions of cycles, lower 32 bits
* represent cycles. However, we use timespec64_to_ns for the * represent cycles. However, we use timespec64_to_ns for the
* correct math even though the units haven't been corrected * correct math even though the units haven't been corrected
...@@ -921,6 +922,7 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, ...@@ -921,6 +922,7 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
switch (hw->mac.type) { switch (hw->mac.type) {
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
/* enable timestamping all packets only if at least some /* enable timestamping all packets only if at least some
* packets were requested. Otherwise, play nice and disable * packets were requested. Otherwise, play nice and disable
* timestamping * timestamping
...@@ -1083,6 +1085,7 @@ void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter) ...@@ -1083,6 +1085,7 @@ void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
cc.shift = 2; cc.shift = 2;
} }
/* fallthrough */ /* fallthrough */
case ixgbe_mac_x550em_a:
case ixgbe_mac_X550: case ixgbe_mac_X550:
cc.read = ixgbe_ptp_read_X550; cc.read = ixgbe_ptp_read_X550;
...@@ -1223,6 +1226,7 @@ static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter) ...@@ -1223,6 +1226,7 @@ static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
break; break;
case ixgbe_mac_X550: case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_x:
case ixgbe_mac_x550em_a:
snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name); snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
adapter->ptp_caps.owner = THIS_MODULE; adapter->ptp_caps.owner = THIS_MODULE;
adapter->ptp_caps.max_adj = 30000000; adapter->ptp_caps.max_adj = 30000000;
......
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
View file @ 70f767d3
...@@ -75,21 +75,29 @@ ...@@ -75,21 +75,29 @@
#define IXGBE_DEV_ID_X540T1 0x1560 #define IXGBE_DEV_ID_X540T1 0x1560
#define IXGBE_DEV_ID_X550T 0x1563 #define IXGBE_DEV_ID_X550T 0x1563
#define IXGBE_DEV_ID_X550T1 0x15D1
#define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA #define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA
#define IXGBE_DEV_ID_X550EM_X_KR 0x15AB #define IXGBE_DEV_ID_X550EM_X_KR 0x15AB
#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC #define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD #define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE #define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE
#define IXGBE_DEV_ID_X550EM_A_KR 0x15C2
#define IXGBE_DEV_ID_X550EM_A_KR_L 0x15C3
#define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4
#define IXGBE_DEV_ID_X550EM_A_SGMII 0x15C6
#define IXGBE_DEV_ID_X550EM_A_SGMII_L 0x15C7
#define IXGBE_DEV_ID_X550EM_A_SFP 0x15CE
/* VF Device IDs */
#define IXGBE_DEV_ID_X550_VF_HV 0x1564 #define IXGBE_DEV_ID_X550_VF_HV 0x1564
#define IXGBE_DEV_ID_X550_VF 0x1565 #define IXGBE_DEV_ID_X550_VF 0x1565
#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9 #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
/* VF Device IDs */
#define IXGBE_DEV_ID_82599_VF 0x10ED #define IXGBE_DEV_ID_82599_VF 0x10ED
#define IXGBE_DEV_ID_X540_VF 0x1515 #define IXGBE_DEV_ID_X540_VF 0x1515
#define IXGBE_DEV_ID_X550_VF 0x1565 #define IXGBE_DEV_ID_X550_VF 0x1565
#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
#define IXGBE_DEV_ID_X550EM_A_VF 0x15C5
#define IXGBE_CAT(r, m) IXGBE_##r##_##m #define IXGBE_CAT(r, m) IXGBE_##r##_##m
...@@ -128,7 +136,7 @@ ...@@ -128,7 +136,7 @@
#define IXGBE_FLA_X540 IXGBE_FLA_8259X #define IXGBE_FLA_X540 IXGBE_FLA_8259X
#define IXGBE_FLA_X550 IXGBE_FLA_8259X #define IXGBE_FLA_X550 IXGBE_FLA_8259X
#define IXGBE_FLA_X550EM_x IXGBE_FLA_8259X #define IXGBE_FLA_X550EM_x IXGBE_FLA_8259X
#define IXGBE_FLA_X550EM_a 0x15F6C #define IXGBE_FLA_X550EM_a 0x15F68
#define IXGBE_FLA(_hw) IXGBE_BY_MAC((_hw), FLA) #define IXGBE_FLA(_hw) IXGBE_BY_MAC((_hw), FLA)
#define IXGBE_EEMNGCTL 0x10110 #define IXGBE_EEMNGCTL 0x10110
#define IXGBE_EEMNGDATA 0x10114 #define IXGBE_EEMNGDATA 0x10114
...@@ -143,13 +151,6 @@ ...@@ -143,13 +151,6 @@
#define IXGBE_GRC_X550EM_a 0x15F64 #define IXGBE_GRC_X550EM_a 0x15F64
#define IXGBE_GRC(_hw) IXGBE_BY_MAC((_hw), GRC) #define IXGBE_GRC(_hw) IXGBE_BY_MAC((_hw), GRC)
#define IXGBE_SRAMREL_8259X 0x10210
#define IXGBE_SRAMREL_X540 IXGBE_SRAMREL_8259X
#define IXGBE_SRAMREL_X550 IXGBE_SRAMREL_8259X
#define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL_8259X
#define IXGBE_SRAMREL_X550EM_a 0x15F6C
#define IXGBE_SRAMREL(_hw) IXGBE_BY_MAC((_hw), SRAMREL)
/* General Receive Control */ /* General Receive Control */
#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
...@@ -375,6 +376,8 @@ struct ixgbe_thermal_sensor_data { ...@@ -375,6 +376,8 @@ struct ixgbe_thermal_sensor_data {
#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) #define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
#define IXGBE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4)) /* 4 total */
#define IXGBE_WQBR_TX(_i) (0x8130 + ((_i) * 4)) /* 4 total */
#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
#define IXGBE_RXFECCERR0 0x051B8 #define IXGBE_RXFECCERR0 0x051B8
#define IXGBE_LLITHRESH 0x0EC90 #define IXGBE_LLITHRESH 0x0EC90
...@@ -446,6 +449,8 @@ struct ixgbe_thermal_sensor_data { ...@@ -446,6 +449,8 @@ struct ixgbe_thermal_sensor_data {
#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
#define IXGBE_DMATXCTL_MDP_EN 0x20 /* Bit 5 */
#define IXGBE_DMATXCTL_MBINTEN 0x40 /* Bit 6 */
#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
...@@ -554,7 +559,6 @@ struct ixgbe_thermal_sensor_data { ...@@ -554,7 +559,6 @@ struct ixgbe_thermal_sensor_data {
#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
/* Security Control Registers */ /* Security Control Registers */
#define IXGBE_SECTXCTRL 0x08800 #define IXGBE_SECTXCTRL 0x08800
#define IXGBE_SECTXSTAT 0x08804 #define IXGBE_SECTXSTAT 0x08804
...@@ -1203,6 +1207,8 @@ struct ixgbe_thermal_sensor_data { ...@@ -1203,6 +1207,8 @@ struct ixgbe_thermal_sensor_data {
#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */ #define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */
#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */ #define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */
#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */ #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */
#define IXGBE_RDRXCTL_MBINTEN 0x10000000
#define IXGBE_RDRXCTL_MDP_EN 0x20000000
/* RQTC Bit Masks and Shifts */ /* RQTC Bit Masks and Shifts */
#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
...@@ -1309,6 +1315,7 @@ struct ixgbe_thermal_sensor_data { ...@@ -1309,6 +1315,7 @@ struct ixgbe_thermal_sensor_data {
/* MDIO definitions */ /* MDIO definitions */
#define IXGBE_MDIO_ZERO_DEV_TYPE 0x0
#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
#define IXGBE_MDIO_PCS_DEV_TYPE 0x3 #define IXGBE_MDIO_PCS_DEV_TYPE 0x3
#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 #define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
...@@ -1957,7 +1964,9 @@ enum { ...@@ -1957,7 +1964,9 @@ enum {
#define IXGBE_GSSR_PHY1_SM 0x0004 #define IXGBE_GSSR_PHY1_SM 0x0004
#define IXGBE_GSSR_MAC_CSR_SM 0x0008 #define IXGBE_GSSR_MAC_CSR_SM 0x0008
#define IXGBE_GSSR_FLASH_SM 0x0010 #define IXGBE_GSSR_FLASH_SM 0x0010
#define IXGBE_GSSR_NVM_UPDATE_SM 0x0200
#define IXGBE_GSSR_SW_MNG_SM 0x0400 #define IXGBE_GSSR_SW_MNG_SM 0x0400
#define IXGBE_GSSR_TOKEN_SM 0x40000000 /* SW bit for shared access */
#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys & I2Cs */ #define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys & I2Cs */
#define IXGBE_GSSR_I2C_MASK 0x1800 #define IXGBE_GSSR_I2C_MASK 0x1800
#define IXGBE_GSSR_NVM_PHY_MASK 0xF #define IXGBE_GSSR_NVM_PHY_MASK 0xF
...@@ -1997,6 +2006,9 @@ enum { ...@@ -1997,6 +2006,9 @@ enum {
#define IXGBE_PBANUM_PTR_GUARD 0xFAFA #define IXGBE_PBANUM_PTR_GUARD 0xFAFA
#define IXGBE_EEPROM_CHECKSUM 0x3F #define IXGBE_EEPROM_CHECKSUM 0x3F
#define IXGBE_EEPROM_SUM 0xBABA #define IXGBE_EEPROM_SUM 0xBABA
#define IXGBE_EEPROM_CTRL_4 0x45
#define IXGBE_EE_CTRL_4_INST_ID 0x10
#define IXGBE_EE_CTRL_4_INST_ID_SHIFT 4
#define IXGBE_PCIE_ANALOG_PTR 0x03 #define IXGBE_PCIE_ANALOG_PTR 0x03
#define IXGBE_ATLAS0_CONFIG_PTR 0x04 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
#define IXGBE_PHY_PTR 0x04 #define IXGBE_PHY_PTR 0x04
...@@ -2530,6 +2542,10 @@ enum ixgbe_fdir_pballoc_type { ...@@ -2530,6 +2542,10 @@ enum ixgbe_fdir_pballoc_type {
#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
#define IXGBE_FDIRCTRL_FLEX_SHIFT 16 #define IXGBE_FDIRCTRL_FLEX_SHIFT 16
#define IXGBE_FDIRCTRL_DROP_NO_MATCH 0x00008000
#define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21
#define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001 /* bit 23:21, 001b */
#define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002 /* bit 23:21, 010b */
#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
...@@ -2620,6 +2636,20 @@ enum ixgbe_fdir_pballoc_type { ...@@ -2620,6 +2636,20 @@ enum ixgbe_fdir_pballoc_type {
#define FW_MAX_READ_BUFFER_SIZE 1024 #define FW_MAX_READ_BUFFER_SIZE 1024
#define FW_DISABLE_RXEN_CMD 0xDE #define FW_DISABLE_RXEN_CMD 0xDE
#define FW_DISABLE_RXEN_LEN 0x1 #define FW_DISABLE_RXEN_LEN 0x1
#define FW_PHY_MGMT_REQ_CMD 0x20
#define FW_PHY_TOKEN_REQ_CMD 0x0A
#define FW_PHY_TOKEN_REQ_LEN 2
#define FW_PHY_TOKEN_REQ 0
#define FW_PHY_TOKEN_REL 1
#define FW_PHY_TOKEN_OK 1
#define FW_PHY_TOKEN_RETRY 0x80
#define FW_PHY_TOKEN_DELAY 5 /* milliseconds */
#define FW_PHY_TOKEN_WAIT 5 /* seconds */
#define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)
#define FW_INT_PHY_REQ_CMD 0xB
#define FW_INT_PHY_REQ_LEN 10
#define FW_INT_PHY_REQ_READ 0
#define FW_INT_PHY_REQ_WRITE 1
/* Host Interface Command Structures */ /* Host Interface Command Structures */
struct ixgbe_hic_hdr { struct ixgbe_hic_hdr {
...@@ -2688,6 +2718,28 @@ struct ixgbe_hic_disable_rxen { ...@@ -2688,6 +2718,28 @@ struct ixgbe_hic_disable_rxen {
u16 pad3; u16 pad3;
}; };
struct ixgbe_hic_phy_token_req {
struct ixgbe_hic_hdr hdr;
u8 port_number;
u8 command_type;
u16 pad;
};
struct ixgbe_hic_internal_phy_req {
struct ixgbe_hic_hdr hdr;
u8 port_number;
u8 command_type;
__be16 address;
u16 rsv1;
__be32 write_data;
u16 pad;
} __packed;
struct ixgbe_hic_internal_phy_resp {
struct ixgbe_hic_hdr hdr;
__be32 read_data;
};
/* Transmit Descriptor - Advanced */ /* Transmit Descriptor - Advanced */
union ixgbe_adv_tx_desc { union ixgbe_adv_tx_desc {
struct { struct {
...@@ -2948,7 +3000,6 @@ union ixgbe_atr_hash_dword { ...@@ -2948,7 +3000,6 @@ union ixgbe_atr_hash_dword {
IXGBE_CAT(EEC, m), \ IXGBE_CAT(EEC, m), \
IXGBE_CAT(FLA, m), \ IXGBE_CAT(FLA, m), \
IXGBE_CAT(GRC, m), \ IXGBE_CAT(GRC, m), \
IXGBE_CAT(SRAMREL, m), \
IXGBE_CAT(FACTPS, m), \ IXGBE_CAT(FACTPS, m), \
IXGBE_CAT(SWSM, m), \ IXGBE_CAT(SWSM, m), \
IXGBE_CAT(SWFW_SYNC, m), \ IXGBE_CAT(SWFW_SYNC, m), \
...@@ -2989,6 +3040,7 @@ enum ixgbe_mac_type { ...@@ -2989,6 +3040,7 @@ enum ixgbe_mac_type {
ixgbe_mac_X540, ixgbe_mac_X540,
ixgbe_mac_X550, ixgbe_mac_X550,
ixgbe_mac_X550EM_x, ixgbe_mac_X550EM_x,
ixgbe_mac_x550em_a,
ixgbe_num_macs ixgbe_num_macs
}; };
...@@ -3017,6 +3069,7 @@ enum ixgbe_phy_type { ...@@ -3017,6 +3069,7 @@ enum ixgbe_phy_type {
ixgbe_phy_qsfp_intel, ixgbe_phy_qsfp_intel,
ixgbe_phy_qsfp_unknown, ixgbe_phy_qsfp_unknown,
ixgbe_phy_sfp_unsupported, ixgbe_phy_sfp_unsupported,
ixgbe_phy_sgmii,
ixgbe_phy_generic ixgbe_phy_generic
}; };
...@@ -3130,8 +3183,9 @@ struct ixgbe_bus_info { ...@@ -3130,8 +3183,9 @@ struct ixgbe_bus_info {
enum ixgbe_bus_width width; enum ixgbe_bus_width width;
enum ixgbe_bus_type type; enum ixgbe_bus_type type;
u16 func; u8 func;
u16 lan_id; u8 lan_id;
u8 instance_id;
}; };
/* Flow control parameters */ /* Flow control parameters */
...@@ -3325,6 +3379,8 @@ struct ixgbe_mac_operations { ...@@ -3325,6 +3379,8 @@ struct ixgbe_mac_operations {
s32 (*dmac_config)(struct ixgbe_hw *hw); s32 (*dmac_config)(struct ixgbe_hw *hw);
s32 (*dmac_update_tcs)(struct ixgbe_hw *hw); s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
s32 (*dmac_config_tcs)(struct ixgbe_hw *hw); s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);
s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *);
s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32);
}; };
struct ixgbe_phy_operations { struct ixgbe_phy_operations {
...@@ -3519,6 +3575,8 @@ struct ixgbe_info { ...@@ -3519,6 +3575,8 @@ struct ixgbe_info {
#define IXGBE_ERR_INVALID_ARGUMENT -32 #define IXGBE_ERR_INVALID_ARGUMENT -32
#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33 #define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
#define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38 #define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38
#define IXGBE_ERR_FW_RESP_INVALID -39
#define IXGBE_ERR_TOKEN_RETRY -40
#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4)) #define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
...@@ -3528,6 +3586,8 @@ struct ixgbe_info { ...@@ -3528,6 +3586,8 @@ struct ixgbe_info {
#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010) #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C) #define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
#define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C) #define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C)
#define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248)
#define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0)
#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634) #define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638) #define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00) #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
...@@ -3541,6 +3601,8 @@ struct ixgbe_info { ...@@ -3541,6 +3601,8 @@ struct ixgbe_info {
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8) #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8) #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8)
#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8) #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN BIT(12)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN BIT(13)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14) #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15) #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15)
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16) #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16)
...@@ -3553,6 +3615,12 @@ struct ixgbe_info { ...@@ -3553,6 +3615,12 @@ struct ixgbe_info {
#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28) #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28)
#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29) #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29)
#define IXGBE_KRM_AN_CNTL_8_LINEAR BIT(0)
#define IXGBE_KRM_AN_CNTL_8_LIMITING BIT(1)
#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D BIT(12)
#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D BIT(19)
#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6) #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6)
#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15) #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15)
#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16) #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16)
...@@ -3597,5 +3665,10 @@ struct ixgbe_info { ...@@ -3597,5 +3665,10 @@ struct ixgbe_info {
#define IXGBE_SB_IOSF_TARGET_KX4_PCS1 3 #define IXGBE_SB_IOSF_TARGET_KX4_PCS1 3
#define IXGBE_NW_MNG_IF_SEL 0x00011178 #define IXGBE_NW_MNG_IF_SEL 0x00011178
#define IXGBE_NW_MNG_IF_SEL_MDIO_ACT BIT(1)
#define IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M BIT(23)
#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE BIT(24) #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE BIT(24)
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \
(0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
#endif /* _IXGBE_TYPE_H_ */ #endif /* _IXGBE_TYPE_H_ */
drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c
View file @ 70f767d3
...@@ -288,9 +288,10 @@ static void ixgbevf_tx_timeout(struct net_device *netdev) ...@@ -288,9 +288,10 @@ static void ixgbevf_tx_timeout(struct net_device *netdev)
* ixgbevf_clean_tx_irq - Reclaim resources after transmit completes * ixgbevf_clean_tx_irq - Reclaim resources after transmit completes
* @q_vector: board private structure * @q_vector: board private structure
* @tx_ring: tx ring to clean * @tx_ring: tx ring to clean
* @napi_budget: Used to determine if we are in netpoll
**/ **/
static bool ixgbevf_clean_tx_irq(struct ixgbevf_q_vector *q_vector, static bool ixgbevf_clean_tx_irq(struct ixgbevf_q_vector *q_vector,
struct ixgbevf_ring *tx_ring) struct ixgbevf_ring *tx_ring, int napi_budget)
{ {
struct ixgbevf_adapter *adapter = q_vector->adapter; struct ixgbevf_adapter *adapter = q_vector->adapter;
struct ixgbevf_tx_buffer *tx_buffer; struct ixgbevf_tx_buffer *tx_buffer;
...@@ -328,7 +329,7 @@ static bool ixgbevf_clean_tx_irq(struct ixgbevf_q_vector *q_vector, ...@@ -328,7 +329,7 @@ static bool ixgbevf_clean_tx_irq(struct ixgbevf_q_vector *q_vector,
total_packets += tx_buffer->gso_segs; total_packets += tx_buffer->gso_segs;
/* free the skb */ /* free the skb */
dev_kfree_skb_any(tx_buffer->skb); napi_consume_skb(tx_buffer->skb, napi_budget);
/* unmap skb header data */ /* unmap skb header data */
dma_unmap_single(tx_ring->dev, dma_unmap_single(tx_ring->dev,
...@@ -1013,8 +1014,10 @@ static int ixgbevf_poll(struct napi_struct *napi, int budget) ...@@ -1013,8 +1014,10 @@ static int ixgbevf_poll(struct napi_struct *napi, int budget)
int per_ring_budget, work_done = 0; int per_ring_budget, work_done = 0;
bool clean_complete = true; bool clean_complete = true;
ixgbevf_for_each_ring(ring, q_vector->tx) ixgbevf_for_each_ring(ring, q_vector->tx) {
clean_complete &= ixgbevf_clean_tx_irq(q_vector, ring); if (!ixgbevf_clean_tx_irq(q_vector, ring, budget))
clean_complete = false;
}
if (budget <= 0) if (budget <= 0)
return budget; return budget;
...@@ -1035,7 +1038,8 @@ static int ixgbevf_poll(struct napi_struct *napi, int budget) ...@@ -1035,7 +1038,8 @@ static int ixgbevf_poll(struct napi_struct *napi, int budget)
int cleaned = ixgbevf_clean_rx_irq(q_vector, ring, int cleaned = ixgbevf_clean_rx_irq(q_vector, ring,
per_ring_budget); per_ring_budget);
work_done += cleaned; work_done += cleaned;
clean_complete &= (cleaned < per_ring_budget); if (cleaned >= per_ring_budget)
clean_complete = false;
} }
#ifdef CONFIG_NET_RX_BUSY_POLL #ifdef CONFIG_NET_RX_BUSY_POLL
......
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