drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications

Writes to CURSURFLIVE in TGL are causing IOMMU errors and visual
glitches that are often reproduced when executing CPU intensive
workloads while a eDP 4K panel is attached.

Manually exiting PSR causes the frontbuffer to be updated without
glitches and the IOMMU errors are also gone but this comes at the cost
of less time with PSR active.

So using this workaround until this issue is root caused and a better
fix is found.

The current code is already ready to enable PSR after this exit if
there is not other frontbuffer modifications.

Adding a new if block in psr_force_hw_tracking_exit() instead of reuse
the else/gen8- block because the plan is to revert this workaround
as soon as a better solution is found.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Tested-by: default avatarGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: default avatarGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201002231627.24528-1-jose.souza@intel.com
parent e44adb5d
......@@ -1147,7 +1147,21 @@ void intel_psr_disable(struct intel_dp *intel_dp,
static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
{
if (INTEL_GEN(dev_priv) >= 9)
if (IS_TIGERLAKE(dev_priv))
/*
* Writes to CURSURFLIVE in TGL are causing IOMMU errors and
* visual glitches that are often reproduced when executing
* CPU intensive workloads while a eDP 4K panel is attached.
*
* Manually exiting PSR causes the frontbuffer to be updated
* without glitches and the IOMMU errors are also gone but
* this comes at the cost of less time with PSR active.
*
* So using this workaround until this issue is root caused
* and a better fix is found.
*/
intel_psr_exit(dev_priv);
else if (INTEL_GEN(dev_priv) >= 9)
/*
* Display WA #0884: skl+
* This documented WA for bxt can be safely applied
......
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