arm64: dts: marvell: de-duplicate CP110 description

One concept of Marvell Armada 7K/8K SoCs is that they are made of HW
blocks composed of a variety of IPs (network, PCIe, SATA, XOR, SPI,
I2C, etc.), and those HW blocks can be duplicated several times within
a given SoC. The Armada 7K SoC has a single CP110 (so no duplication),
while the Armada 8K SoC has two CP110. In the future, SoCs with more
than 2 CP110s will be introduced.

In current kernel versions, the master CP110 is described in
armada-cp110-master.dtsi and the slave CP110 is described in
armada-cp110-slave.dtsi. Those files are basically exactly the same,
since they describe the same hardware. They only have a few
differences:

 - Base address of the registers is different for the "config-space"

 - Base address of the PCIe registers, MEM, CONF and IO areas were
   different

 - Labels (and phandles pointing to them) of the nodes were different
   ("cpm" prefix in the master CP, "cps" prefix in the slave CP)

This duplication issue has been discussed at the DT workshop [1] in
Prague last October, and we presented on this topic [2]. The solution
of using the C pre-processor to avoid this duplication has been
validated by the people present in this DT workshop, and this patch
simply implements what has been presented.

We handle differences between the master CP and slave CP description
using the C pre-processor, by defining a set of macros with different
values armada-cp110.dtsi is included to instantiate one of the master
or slave CP110.

There are a few aspects that deserve additional explanations:

 - PCIe needs to be handled separately because it is not part of the
   config-space {...} node, since it has registers outside of the
   range covered by config-space {...}.

 - We need to defined CP110_BASE, CP110_PCIEx_BASE without 0x, because
   they are used for the unit address part of some DT nodes. But since
   they are also used for the "reg" property of the same nodes, we
   have an ADDRESSIFY() macro that prepends 0x to those values.

We compared the resulting .dtb for armada-8040-db.dtb before and after
this patch is applied, and the result is exactly the same, except for
a few differences:

 - the SDHCI controller that was only described in the master CP110 is
   now also described in the slave CP110. Even though the SDHCI
   controller from the slave CP110 is indeed not usable (as it isn't
   wired to the outside world) it is technically part of the silicon,
   and therefore it is reasonable to also describe it to be part of
   the slave CP110. In addition, if we wanted to get this correct for
   the SDHCI controller, we should also do it for the NAND controller,
   for which the situation is even more complicated: in a single CP110
   configuration (Armada 7K), the usable NAND controller is in the
   master CP110, while in a dual CP110 configuration (Armada 8K), the
   usable NAND controller is in the slave CP110. Since that would add
   a lot of additional complexity for no good reason, and since the IP
   blocks are in fact really present in both CPs, we simply describe
   them in both CPs at the DT level.

 - the cp110-master and cp110-slave nodes are now named cpm and
   cps. We could have kept cp110-master and cp110-slave, but that
   would have required adding another CP110_xyz define, which didn't
   seem very useful.

Note that this commit also gets rid of the armada-cp110-master.dtsi
and armada-cp110-slave.dtsi files, as future SoCs will have more than
2 CPs. Instead, we instantiate the CPs directly from the SoC-specific
.dtsi files, i.e armada-70x0.dtsi and armada-80x0.dtsi.

[1] https://elinux.org/Device_tree_kernel_summit_2017_etherpad
[2] https://elinux.org/images/1/14/DTWorkshop2017-duplicate-data.pdf

[gregory.clement@free-electrons.com: add back the "ARM64: dts: marvell:
Fix clock resources for various node" commit]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

arch/arm64/boot/dts/marvell/armada-70x0.dtsi

@@ -44,8 +44,6 @@
  * Device Tree file for the Armada 70x0 SoC
  */
 
-#include "armada-cp110-master.dtsi"
-
 / {
 	aliases {
 		gpio1 = &cpm_gpio1;
@@ -55,6 +53,27 @@ aliases {
 	};
 };
 
+/*
+ * Instantiate the CP110
+ */
+#define CP110_NAME		cpm
+#define CP110_BASE		f2000000
+#define CP110_PCIE_IO_BASE	0xf9000000
+#define CP110_PCIE_MEM_BASE	0xf6000000
+#define CP110_PCIE0_BASE	f2600000
+#define CP110_PCIE1_BASE	f2620000
+#define CP110_PCIE2_BASE	f2640000
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE_IO_BASE
+#undef CP110_PCIE_MEM_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
 &cpm_gpio1 {
 	status = "okay";
 };

arch/arm64/boot/dts/marvell/armada-80x0.dtsi

@@ -44,9 +44,6 @@
  * Device Tree file for the Armada 80x0 SoC family
  */
 
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
-
 / {
 	aliases {
 		gpio1 = &cps_gpio1;
@@ -58,6 +55,48 @@ aliases {
 	};
 };
 
+/*
+ * Instantiate the master CP110
+ */
+#define CP110_NAME		cpm
+#define CP110_BASE		f2000000
+#define CP110_PCIE_IO_BASE	0xf9000000
+#define CP110_PCIE_MEM_BASE	0xf6000000
+#define CP110_PCIE0_BASE	f2600000
+#define CP110_PCIE1_BASE	f2620000
+#define CP110_PCIE2_BASE	f2640000
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE_IO_BASE
+#undef CP110_PCIE_MEM_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
+/*
+ * Instantiate the slave CP110
+ */
+#define CP110_NAME		cps
+#define CP110_BASE		f4000000
+#define CP110_PCIE_IO_BASE	0xfd000000
+#define CP110_PCIE_MEM_BASE	0xfa000000
+#define CP110_PCIE0_BASE	f4600000
+#define CP110_PCIE1_BASE	f4620000
+#define CP110_PCIE2_BASE	f4640000
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE_IO_BASE
+#undef CP110_PCIE_MEM_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
 /* The 80x0 has two CP blocks, but uses only one block from each. */
 &cps_gpio1 {
 	status = "okay";
@@ -95,3 +134,14 @@ nand_rb: nand-rb {
 		};
 	};
 };
+
+&cps_crypto {
+	/*
+	 * The cryptographic engine found on the cp110
+	 * master is enabled by default at the SoC
+	 * level. Because it is not possible as of now
+	 * to enable two cryptographic engines in
+	 * parallel, disable this one by default.
+	 */
+	status = "disabled";
+};

arch/arm64/boot/dts/marvell/armada-common.dtsi

+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ */
+
+/* Common definitions used by Armada 7K/8K DTs */
+#define PASTER(x, y) x ## y
+#define EVALUATOR(x, y) PASTER(x, y)
+#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
+#define ADDRESSIFY(addr) EVALUATOR(0x, addr)