Commit 72af17b9 authored by Antoine Tenart's avatar Antoine Tenart Committed by Gregory CLEMENT

arm64: dts: marvell: mcbin: enable more networking ports

This patch enables the two GE/SFP ports. They are configured in 10GKR
mode by default. To do this the cpm_xdmio is enabled as well, and two
phy descriptions are added.
Signed-off-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Tested-by: default avatarMarcin Wojtas <mw@semihalf.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 791b0ade
...@@ -202,6 +202,30 @@ cpm_sdhci_pins: sdhci-pins { ...@@ -202,6 +202,30 @@ cpm_sdhci_pins: sdhci-pins {
}; };
}; };
&cpm_xmdio {
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
phy8: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cpm_ethernet {
status = "okay";
};
&cpm_eth0 {
status = "okay";
phy = <&phy0>;
phy-mode = "10gbase-kr";
};
&cpm_sata0 { &cpm_sata0 {
/* CPM Lane 0 - U29 */ /* CPM Lane 0 - U29 */
status = "okay"; status = "okay";
...@@ -231,6 +255,12 @@ &cps_ethernet { ...@@ -231,6 +255,12 @@ &cps_ethernet {
status = "okay"; status = "okay";
}; };
&cps_eth0 {
status = "okay";
phy = <&phy8>;
phy-mode = "10gbase-kr";
};
&cps_eth1 { &cps_eth1 {
/* CPS Lane 0 - J5 (Gigabit RJ45) */ /* CPS Lane 0 - J5 (Gigabit RJ45) */
status = "okay"; status = "okay";
......
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