Commit 738a368d authored by Fabrizio Castro's avatar Fabrizio Castro Committed by Simon Horman

ARM: dts: iwg22d-sodimm: sort dt nodes

Improve the layout of r8a7745-iwg22d-sodimm.dts by sorting the
nodes alphabetically.
Signed-off-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: default avatarChris Paterson <chris.paterson2@renesas.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent ea03afbe
...@@ -16,9 +16,9 @@ / { ...@@ -16,9 +16,9 @@ / {
compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745";
aliases { aliases {
ethernet0 = &avb;
serial3 = &scif4; serial3 = &scif4;
serial5 = &hscif1; serial5 = &hscif1;
ethernet0 = &avb;
}; };
chosen { chosen {
...@@ -40,6 +40,25 @@ vccq_sdhi0: regulator-vccq-sdhi0 { ...@@ -40,6 +40,25 @@ vccq_sdhi0: regulator-vccq-sdhi0 {
}; };
}; };
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy3>;
phy-mode = "gmii";
renesas,no-ether-link;
status = "okay";
phy3: ethernet-phy@3 {
/*
* On some older versions of the platform (before R4.0) the phy address
* may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
*/
reg = <3>;
micrel,led-mode = <1>;
};
};
&hscif1 { &hscif1 {
pinctrl-0 = <&hscif1_pins>; pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -48,7 +67,18 @@ &hscif1 { ...@@ -48,7 +67,18 @@ &hscif1 {
status = "okay"; status = "okay";
}; };
&pci1 {
status = "okay";
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
};
&pfc { &pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_gmii";
function = "avb";
};
hscif1_pins: hscif1 { hscif1_pins: hscif1 {
groups = "hscif1_data", "hscif1_ctrl"; groups = "hscif1_data", "hscif1_ctrl";
function = "hscif1"; function = "hscif1";
...@@ -59,11 +89,6 @@ scif4_pins: scif4 { ...@@ -59,11 +89,6 @@ scif4_pins: scif4 {
function = "scif4"; function = "scif4";
}; };
avb_pins: avb {
groups = "avb_mdio", "avb_gmii";
function = "avb";
};
sdhi0_pins: sd0 { sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl"; groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0"; function = "sdhi0";
...@@ -83,25 +108,6 @@ &scif4 { ...@@ -83,25 +108,6 @@ &scif4 {
status = "okay"; status = "okay";
}; };
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy3>;
phy-mode = "gmii";
renesas,no-ether-link;
status = "okay";
phy3: ethernet-phy@3 {
/*
* On some older versions of the platform (before R4.0) the phy address
* may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
*/
reg = <3>;
micrel,led-mode = <1>;
};
};
&sdhi0 { &sdhi0 {
pinctrl-0 = <&sdhi0_pins>; pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -112,12 +118,6 @@ &sdhi0 { ...@@ -112,12 +118,6 @@ &sdhi0 {
status = "okay"; status = "okay";
}; };
&pci1 {
status = "okay";
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
};
&usbphy { &usbphy {
status = "okay"; status = "okay";
}; };
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