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Commit 75006b98 authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://bk.arm.linux.org.uk/linux-2.5-rmk 

into home.transmeta.com:/home/torvalds/v2.5/linux
parents 782ed19e d76641fa
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Showing with 167 additions and 18 deletions
arch/arm/Kconfig
View file @ 75006b98
......@@ -377,6 +377,15 @@ config ARM_THUMB
If you don't know what this all is, saying Y is a safe choice.
config CPU_BIG_ENDIAN
bool "Build big-endian kernel"
depends on ARCH_SUPPORTS_BIG_ENDIAN
help
Say Y if you plan on running a kernel in big-endian mode.
Note that your board must be properly built and your board
port must properly enable and big-endian related features
of your chipset/board/processor.
config CPU_ICACHE_DISABLE
bool "Disable I-Cache"
depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM926T || CPU_ARM1020
......
arch/arm/Makefile
View file @ 75006b98
......@@ -24,6 +24,12 @@ ifeq ($(CONFIG_DEBUG_INFO),y)
CFLAGS +=-g
endif
ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
CFLAGS += -mbig-endian
AS += -EB
LD += -EB
endif
# Select CPU dependent flags. Note that order of declaration is important;
# the options further down the list override previous items.
#
......@@ -34,10 +40,7 @@ apcs-$(CONFIG_CPU_26) :=-mapcs-26 -mcpu=arm3
# Note that GCC does not numerically define an architecture version
# macro, but instead defines a whole series of macros which makes
# testing for a specific architecture or later rather impossible.
#
# Note - GCC does accept -march=armv5te, but someone messed up the assembler or the
# gcc specs file - this needs fixing properly - ie in gcc and/or binutils.
arch-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5 -march=armv5t
arch-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5 -march=armv5te
arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4
arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3
......@@ -50,13 +53,13 @@ tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110
tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100
tune-$(CONFIG_CPU_XSCALE) :=-mtune=strongarm -Wa,-mxscale #-mtune=xscale
tune-$(CONFIG_CPU_XSCALE) :=-mtune=xscale
# Force -mno-fpu to be passed to the assembler. Some versions of gcc don't
# do this with -msoft-float
CFLAGS_BOOT :=$(apcs-y) $(arch-y) $(tune-y) -mshort-load-bytes -msoft-float -Wa,-mno-fpu -Uarm
CFLAGS +=$(apcs-y) $(arch-y) $(tune-y) -mshort-load-bytes -msoft-float -Wa,-mno-fpu -Uarm
AFLAGS +=$(apcs-y) $(arch-y) $(tune-y) -mno-fpu -msoft-float -Wa,-mno-fpu
AFLAGS +=$(apcs-y) $(arch-y) $(tune-y) -msoft-float -Wa,-mno-fpu
#Default value
DATAADDR := .
......@@ -76,7 +79,11 @@ endif
ifeq ($(CONFIG_CPU_32),y)
PROCESSOR := armv
head-y := arch/arm/kernel/head.o arch/arm/kernel/init_task.o
LDFLAGS_BLOB += --oformat elf32-littlearm
ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
LDFLAGS_BLOB += --oformat elf32-bigarm
else
LDFLAGS_BLOB += --oformat elf32-littlearm
endif
textaddr-y := 0xC0008000
endif
......
arch/arm/lib/div64.S
View file @ 75006b98
#include <linux/linkage.h>
#ifndef __ARMEB__
ql .req r0 @ quotient low
qh .req r1 @ quotient high
dl .req r3 @ divisor low
dh .req r2 @ divisor high
onl .req r0 @ original dividend low
onh .req r1 @ original dividend high
nl .req r4 @ dividend low
nh .req r5 @ dividend high
res .req r4 @ result
#else
ql .req r1
qh .req r0
onl .req r1
onh .req r0
nl .req r5
nh .req r4
res .req r5
#endif
dl .req r3 @ divisor low
dh .req r2 @ divsor high
ENTRY(do_div64)
stmfd sp!, {r4, r5, lr}
mov nl, r0
movs nh, r1 @ if high bits are zero
mov nl, onl
movs nh, onh @ if high bits are zero
movne lr, #33
moveq lr, #1 @ only divide low bits
moveq nh, r0
moveq nh, onl
1: cmp nh, dh
bls 2f
add lr, lr, #1
movs dh, dh, lsl #1 @ left justify divisor
movs dh, dh, lsl #1 @ left justify disor
bpl 1b
2: movs nh, r1
2: movs nh, onh
moveq dl, dh
moveq dh, #0
movne dl, #0
......@@ -38,5 +53,5 @@ ENTRY(do_div64)
subs lr, lr, #1
bne 3b
mov r2, nl
mov r2, res
ldmfd sp!, {r4, r5, pc}
include/asm-arm/arch-iop3xx/iop321.h
View file @ 75006b98
......@@ -14,9 +14,16 @@
#ifndef _IOP321_HW_H_
#define _IOP321_HW_H_
#ifndef __ASSEMBLY__
#define iop_is_321() ((processor_id & 0xfffff7e0) == 0x69052420)
#endif
/*
* IOP321 I/O and Mem space regions for PCI autoconfiguration
*/
#define IOP321_PCI_IO_BASE 0x90000000
#define IOP321_PCI_IO_SIZE 0x00010000
#define IOP321_PCI_MEM_BASE 0x40000000
......@@ -26,6 +33,7 @@
* IOP321 chipset registers
*/
#define IOP321_VIRT_MEM_BASE 0xfff00000 /* chip virtual mem address*/
#define IOP321_PHY_MEM_BASE 0xffffe000 /* chip physical memory address */
#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
......@@ -97,12 +105,93 @@
#define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC)
/* Messaging Unit 0x00000300 through 0x000003FF */
/* Reserved 0x00000300 through 0x0000030c */
#define IOP321_IMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000310)
#define IOP321_IMR1 (volatile u32 *)IOP321_REG_ADDR(0x00000314)
#define IOP321_OMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000318)
#define IOP321_OMR1 (volatile u32 *)IOP321_REG_ADDR(0x0000031C)
#define IOP321_IDR (volatile u32 *)IOP321_REG_ADDR(0x00000320)
#define IOP321_IISR (volatile u32 *)IOP321_REG_ADDR(0x00000324)
#define IOP321_IIMR (volatile u32 *)IOP321_REG_ADDR(0x00000328)
#define IOP321_ODR (volatile u32 *)IOP321_REG_ADDR(0x0000032C)
#define IOP321_OISR (volatile u32 *)IOP321_REG_ADDR(0x00000330)
#define IOP321_OIMR (volatile u32 *)IOP321_REG_ADDR(0x00000334)
/* Reserved 0x00000338 through 0x0000034F */
#define IOP321_MUCR (volatile u32 *)IOP321_REG_ADDR(0x00000350)
#define IOP321_QBAR (volatile u32 *)IOP321_REG_ADDR(0x00000354)
/* Reserved 0x00000358 through 0x0000035C */
#define IOP321_IFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000360)
#define IOP321_IFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000364)
#define IOP321_IPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000368)
#define IOP321_IPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000036C)
#define IOP321_OFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000370)
#define IOP321_OFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000374)
#define IOP321_OPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000378)
#define IOP321_OPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000037C)
#define IOP321_IAR (volatile u32 *)IOP321_REG_ADDR(0x00000380)
/* Reserved 0x00000384 through 0x000003FF */
/* DMA Controller 0x00000400 through 0x000004FF */
#define IOP321_DMA0_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000400)
#define IOP321_DMA0_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000404)
#define IOP321_DMA0_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000040C)
#define IOP321_DMA0_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000410)
#define IOP321_DMA0_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000414)
#define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418)
#define IOP321_DMA0_LADR (volatile u32 *)IOP321_REG_ADDR(0X0000041C)
#define IOP321_DMA0_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000420)
#define IOP321_DMA0_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000424)
/* Reserved 0x00000428 through 0x0000043C */
#define IOP321_DMA1_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000440)
#define IOP321_DMA1_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000444)
#define IOP321_DMA1_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000044C)
#define IOP321_DMA1_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000450)
#define IOP321_DMA1_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000454)
#define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458)
#define IOP321_DMA1_LADR (volatile u32 *)IOP321_REG_ADDR(0x0000045C)
#define IOP321_DMA1_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000460)
#define IOP321_DMA1_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000464)
/* Reserved 0x00000468 through 0x000004FF */
/* Memory controller 0x00000500 through 0x0005FF */
/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
#define IOP321_PBCR (volatile u32 *)IOP321_REG_ADDR(0x00000680)
#define IOP321_PBISR (volatile u32 *)IOP321_REG_ADDR(0x00000684)
#define IOP321_PBBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000688)
#define IOP321_PBLR0 (volatile u32 *)IOP321_REG_ADDR(0x0000068C)
#define IOP321_PBBAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000690)
#define IOP321_PBLR1 (volatile u32 *)IOP321_REG_ADDR(0x00000694)
#define IOP321_PBBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000698)
#define IOP321_PBLR2 (volatile u32 *)IOP321_REG_ADDR(0x0000069C)
#define IOP321_PBBAR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A0)
#define IOP321_PBLR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A4)
#define IOP321_PBBAR4 (volatile u32 *)IOP321_REG_ADDR(0x000006A8)
#define IOP321_PBLR4 (volatile u32 *)IOP321_REG_ADDR(0x000006AC)
#define IOP321_PBBAR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B0)
#define IOP321_PBLR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B4)
#define IOP321_PBDSCR (volatile u32 *)IOP321_REG_ADDR(0x000006B8)
/* Reserved 0x000006BC */
#define IOP321_PMBR0 (volatile u32 *)IOP321_REG_ADDR(0x000006C0)
/* Reserved 0x000006C4 through 0x000006DC */
#define IOP321_PMBR1 (volatile u32 *)IOP321_REG_ADDR(0x000006E0)
#define IOP321_PMBR2 (volatile u32 *)IOP321_REG_ADDR(0x000006E4)
#define IOP321_PBCR_EN 0x1
#define IOP321_PBISR_BOOR_ERR 0x1
/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
/* Internal arbitration unit 0x00000780 through 0x0007BF */
/* General Purpose I/O Registers */
#define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4)
#define IOP321_GPID (volatile u32 *)IOP321_REG_ADDR(0x000007C8)
#define IOP321_GPOD (volatile u32 *)IOP321_REG_ADDR(0x000007CC)
/* Interrupt Controller */
#define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0)
#define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4)
......@@ -131,11 +220,40 @@
#define IOP321_TU_TISR (volatile u32 *)IOP321_REG_ADDR(0x000007F8)
#define IOP321_TU_WDTCR (volatile u32 *)IOP321_REG_ADDR(0x000007FC)
/* Application accelerator unit 0x00000800 - 0x000008FF */
#define IOP321_AAUACR (volatile u32 *)IOP321_REG_ADDR(0x00000800)
#define IOP321_AAUASR (volatile u32 *)IOP321_REG_ADDR(0x00000804)
#define IOP321_AAUANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C)
#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800)
#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804)
#define IOP321_AAU_ADAR (volatile u32 *)IOP321_REG_ADDR(0x00000808)
#define IOP321_AAU_ANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C)
#define IOP321_AAU_SAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000810)
/* SAR2...SAR32 0x00000814 - 0x000008A4 */
#define IOP321_AAU_DAR (volatile u32 *)IOP321_REG_ADDR(0x00000820)
#define IOP321_AAU_ABCR (volatile u32 *)IOP321_REG_ADDR(0x00000824)
#define IOP321_AAU_ADCR (volatile u32 *)IOP321_REG_ADDR(0x00000828)
#define IOP321_AAU_EDCR0 (volatile u32 *)IOP321_REG_ADDR(0x0000083c)
#define IOP321_AAU_EDCR1 (volatile u32 *)IOP321_REG_ADDR(0x00000860)
#define IOP321_AAU_EDCR2 (volatile u32 *)IOP321_REG_ADDR(0x00000884)
/* SSP serial port unit 0x00001600 - 0x0000167F */
/* I2C bus interface unit 0x00001680 - 0x000016FF */
#define IOP321_ICR0 (volatile u32 *)IOP321_REG_ADDR(0x00001680)
#define IOP321_ISR0 (volatile u32 *)IOP321_REG_ADDR(0x00001684)
#define IOP321_ISAR0 (volatile u32 *)IOP321_REG_ADDR(0x00001688)
#define IOP321_IDBR0 (volatile u32 *)IOP321_REG_ADDR(0x0000168C)
/* Reserved 0x00001690 */
#define IOP321_IBMR0 (volatile u32 *)IOP321_REG_ADDR(0x00001694)
/* Reserved 0x00001698 */
/* Reserved 0x0000169C */
#define IOP321_ICR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A0)
#define IOP321_ISR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A4)
#define IOP321_ISAR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A8)
#define IOP321_IDBR1 (volatile u32 *)IOP321_REG_ADDR(0x000016AC)
#define IOP321_IBMR1 (volatile u32 *)IOP321_REG_ADDR(0x000016B4)
/* Reserved 0x000016B8 through 0x000016FC */
/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
#endif // _IOP321_HW_H_
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