Commit 7558f978 authored by Sowjanya Komatineni's avatar Sowjanya Komatineni Committed by Mark Brown

spi: document tx/rx clock delay properties

Tegra SPI controller has TX and RX trimmers to tuning the delay of
SPI master clock with respect to the data.

TX and RX tap values are based on the platform validation across the
PVT and the trimmer values vary based on the trace lengths to the
corresponding SPI devices.
Signed-off-by: default avatarSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent f1ca9992
...@@ -23,6 +23,18 @@ Required properties: ...@@ -23,6 +23,18 @@ Required properties:
Recommended properties: Recommended properties:
- spi-max-frequency: Definition as per - spi-max-frequency: Definition as per
Documentation/devicetree/bindings/spi/spi-bus.txt Documentation/devicetree/bindings/spi/spi-bus.txt
Optional properties:
- nvidia,tx-clk-tap-delay: Delays the clock going out to the external device
with this tap value. This property is used to tune the outgoing data from
Tegra SPI master with respect to outgoing Tegra SPI master clock.
Tap values vary based on the platform design trace lengths from Tegra SPI
to corresponding slave devices. Valid tap values are from 0 thru 63.
- nvidia,rx-clk-tap-delay: Delays the clock coming in from the external device
with this tap value. This property is used to adjust the Tegra SPI master
clock with respect to the data from the SPI slave device.
Tap values vary based on the platform design trace lengths from Tegra SPI
to corresponding slave devices. Valid tap values are from 0 thru 63.
Example: Example:
spi@7000d600 { spi@7000d600 {
...@@ -38,4 +50,12 @@ spi@7000d600 { ...@@ -38,4 +50,12 @@ spi@7000d600 {
reset-names = "spi"; reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>; dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx"; dma-names = "rx", "tx";
<spi-client>@<bus_num> {
...
...
nvidia,rx-clk-tap-delay = <0>;
nvidia,tx-clk-tap-delay = <16>;
...
};
}; };
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