Commit 75a41826 authored by Thor Thayer's avatar Thor Thayer Committed by Dinh Nguyen

arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries.

Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.

There was a discussion thread on whether this driver should be an mfd driver
or just make use of syscon, which is already a mfd. Ultimately, the
decision to use a simple syscon interface was reached.[1]

[1] https://lkml.org/lkml/2014/7/30/514Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Acked-by: default avatarPavel Machek <pavel@denx.de>
[dinguyen] cleaned-up commit header and remove version history.
Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
parent c6dcb101
Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
The EDAC accesses a range of registers in the SDRAM controller.
Required properties:
- compatible : should contain "altr,sdram-edac";
- altr,sdr-syscon : phandle of the sdr module
- interrupts : Should contain the SDRAM ECC IRQ in the
appropriate format for the IRQ controller.
Example:
sdramedac {
compatible = "altr,sdram-edac";
altr,sdr-syscon = <&sdr>;
interrupts = <0 39 4>;
};
...@@ -607,6 +607,17 @@ gpio2: gpio-controller@0 { ...@@ -607,6 +607,17 @@ gpio2: gpio-controller@0 {
}; };
}; };
sdr: sdr@ffc25000 {
compatible = "syscon";
reg = <0xffc25000 0x1000>;
};
sdramedac {
compatible = "altr,sdram-edac";
altr,sdr-syscon = <&sdr>;
interrupts = <0 39 4>;
};
L2: l2-cache@fffef000 { L2: l2-cache@fffef000 {
compatible = "arm,pl310-cache"; compatible = "arm,pl310-cache";
reg = <0xfffef000 0x1000>; reg = <0xfffef000 0x1000>;
......
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