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Commit 7624fc01 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/mpeg: convert to new-style nvkm_engine 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 6f41c7c5
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Showing with 166 additions and 363 deletions
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
View file @ 7624fc01
......@@ -19,8 +19,6 @@ struct nvkm_engine {
struct list_head contexts;
spinlock_t lock;
void (*tile_prog)(struct nvkm_engine *, int region);
};
struct nvkm_engine_func {
......
drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
View file @ 7624fc01
#ifndef __NVKM_MPEG_H__
#define __NVKM_MPEG_H__
#include <core/engine.h>
struct nvkm_mpeg {
struct nvkm_engine engine;
};
#define nvkm_mpeg_create(p,e,c,d) \
nvkm_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d))
#define nvkm_mpeg_destroy(d) \
nvkm_engine_destroy(&(d)->engine)
#define nvkm_mpeg_init(d) \
nvkm_engine_init_old(&(d)->engine)
#define nvkm_mpeg_fini(d,s) \
nvkm_engine_fini_old(&(d)->engine, (s))
#define _nvkm_mpeg_dtor _nvkm_engine_dtor
#define _nvkm_mpeg_init _nvkm_engine_init
#define _nvkm_mpeg_fini _nvkm_engine_fini
extern struct nvkm_oclass nv31_mpeg_oclass;
extern struct nvkm_oclass nv40_mpeg_oclass;
extern struct nvkm_oclass nv44_mpeg_oclass;
extern struct nvkm_oclass nv50_mpeg_oclass;
extern struct nvkm_oclass g84_mpeg_oclass;
extern struct nvkm_oclass nv40_mpeg_sclass[];
void nv31_mpeg_intr(struct nvkm_subdev *);
void nv31_mpeg_tile_prog(struct nvkm_engine *, int);
int nv31_mpeg_init(struct nvkm_object *);
extern struct nvkm_ofuncs nv50_mpeg_ofuncs;
int nv50_mpeg_context_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
void nv50_mpeg_intr(struct nvkm_subdev *);
int nv50_mpeg_init(struct nvkm_object *);
int nv31_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int nv40_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int nv44_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int nv50_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
int g84_mpeg_new(struct nvkm_device *, int index, struct nvkm_engine **);
#endif
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View file @ 7624fc01
......@@ -381,7 +381,7 @@ nv31_chipset = {
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
.gr = nv30_gr_new,
// .mpeg = nv31_mpeg_new,
.mpeg = nv31_mpeg_new,
.sw = nv10_sw_new,
};
......@@ -403,7 +403,7 @@ nv34_chipset = {
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
.gr = nv34_gr_new,
// .mpeg = nv31_mpeg_new,
.mpeg = nv31_mpeg_new,
.sw = nv10_sw_new,
};
......@@ -446,7 +446,7 @@ nv36_chipset = {
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
.gr = nv35_gr_new,
// .mpeg = nv31_mpeg_new,
.mpeg = nv31_mpeg_new,
.sw = nv10_sw_new,
};
......@@ -470,7 +470,7 @@ nv40_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
.mpeg = nv40_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -495,7 +495,7 @@ nv41_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
.mpeg = nv40_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -520,7 +520,7 @@ nv42_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
.mpeg = nv40_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -545,7 +545,7 @@ nv43_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
.mpeg = nv40_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -570,7 +570,7 @@ nv44_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -595,7 +595,7 @@ nv45_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -620,7 +620,7 @@ nv46_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -645,7 +645,7 @@ nv47_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -670,7 +670,7 @@ nv49_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -695,7 +695,7 @@ nv4a_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -720,7 +720,7 @@ nv4b_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -745,7 +745,7 @@ nv4c_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -770,7 +770,7 @@ nv4e_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -798,7 +798,7 @@ nv50_chipset = {
.dma = nv50_dma_new,
.fifo = nv50_fifo_new,
.gr = nv50_gr_new,
// .mpeg = nv50_mpeg_new,
.mpeg = nv50_mpeg_new,
.pm = nv50_pm_new,
.sw = nv50_sw_new,
};
......@@ -823,7 +823,7 @@ nv63_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -848,7 +848,7 @@ nv67_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -873,7 +873,7 @@ nv68_chipset = {
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
};
......@@ -903,7 +903,7 @@ nv84_chipset = {
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
.gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = g84_vp_new,
......@@ -934,7 +934,7 @@ nv86_chipset = {
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
.gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = g84_vp_new,
......@@ -965,7 +965,7 @@ nv92_chipset = {
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
.gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = g84_vp_new,
......@@ -996,7 +996,7 @@ nv94_chipset = {
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
.gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = g84_vp_new,
......@@ -1025,7 +1025,7 @@ nv96_chipset = {
.fifo = g84_fifo_new,
.gr = g84_gr_new,
.gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
.mpeg = g84_mpeg_new,
.vp = g84_vp_new,
.cipher = g84_cipher_new,
.bsp = g84_bsp_new,
......@@ -1089,7 +1089,7 @@ nva0_chipset = {
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
.gr = gt200_gr_new,
// .mpeg = g84_mpeg_new,
.mpeg = g84_mpeg_new,
.pm = gt200_pm_new,
.sw = nv50_sw_new,
.vp = g84_vp_new,
......@@ -1120,7 +1120,7 @@ nva3_chipset = {
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
.gr = gt215_gr_new,
// .mpeg = g84_mpeg_new,
.mpeg = g84_mpeg_new,
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
.msvld = gt215_msvld_new,
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
View file @ 7624fc01
......@@ -32,13 +32,10 @@ nv30_identify(struct nvkm_device *device)
case 0x35:
break;
case 0x31:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
break;
case 0x36:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
break;
case 0x34:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
break;
default:
return -EINVAL;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
View file @ 7624fc01
......@@ -28,52 +28,36 @@ nv40_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x40:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
break;
case 0x41:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
break;
case 0x42:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
break;
case 0x43:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
break;
case 0x45:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
break;
case 0x47:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
break;
case 0x49:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
break;
case 0x4b:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
break;
case 0x44:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
break;
case 0x46:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
break;
case 0x4a:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
break;
case 0x4c:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
break;
case 0x4e:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
break;
case 0x63:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
break;
case 0x67:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
break;
case 0x68:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
break;
default:
return -EINVAL;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View file @ 7624fc01
......@@ -28,34 +28,26 @@ nv50_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x50:
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
break;
case 0x84:
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
break;
case 0x86:
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
break;
case 0x92:
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
break;
case 0x94:
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
break;
case 0x96:
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
break;
case 0x98:
break;
case 0xa0:
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
break;
case 0xaa:
break;
case 0xac:
break;
case 0xa3:
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
break;
case 0xa5:
break;
......
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c
View file @ 7624fc01
......@@ -27,6 +27,8 @@
static const struct nvkm_engine_func
g84_mpeg = {
.init = nv50_mpeg_init,
.intr = nv50_mpeg_intr,
.cclass = &nv50_mpeg_cclass,
.sclass = {
{ -1, -1, G82_MPEG, &nv31_mpeg_object },
......@@ -34,33 +36,9 @@ g84_mpeg = {
}
};
static int
g84_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
int
g84_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
{
struct nvkm_mpeg *mpeg;
int ret;
ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
*pobject = nv_object(mpeg);
if (ret)
return ret;
mpeg->engine.func = &g84_mpeg;
nv_subdev(mpeg)->unit = 0x00000002;
nv_subdev(mpeg)->intr = nv50_mpeg_intr;
return 0;
return nvkm_engine_new_(&g84_mpeg, device, index, 0x00000002,
true, pmpeg);
}
struct nvkm_oclass
g84_mpeg_oclass = {
.handle = NV_ENGINE(MPEG, 0x84),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = g84_mpeg_ctor,
.dtor = _nvkm_mpeg_dtor,
.init = nv50_mpeg_init,
.fini = _nvkm_mpeg_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
View file @ 7624fc01
......@@ -68,10 +68,10 @@ nv31_mpeg_chan_dtor(struct nvkm_object *object)
struct nv31_mpeg *mpeg = chan->mpeg;
unsigned long flags;
spin_lock_irqsave(&mpeg->base.engine.lock, flags);
spin_lock_irqsave(&mpeg->engine.lock, flags);
if (mpeg->chan == chan)
mpeg->chan = NULL;
spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
return chan;
}
......@@ -97,12 +97,12 @@ nv31_mpeg_chan_new(struct nvkm_fifo_chan *fifoch,
chan->fifo = fifoch;
*pobject = &chan->object;
spin_lock_irqsave(&mpeg->base.engine.lock, flags);
spin_lock_irqsave(&mpeg->engine.lock, flags);
if (!mpeg->chan) {
mpeg->chan = chan;
ret = 0;
}
spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
return ret;
}
......@@ -111,11 +111,10 @@ nv31_mpeg_chan_new(struct nvkm_fifo_chan *fifoch,
******************************************************************************/
void
nv31_mpeg_tile_prog(struct nvkm_engine *engine, int i)
nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile)
{
struct nv31_mpeg *mpeg = (void *)engine;
struct nvkm_device *device = mpeg->base.engine.subdev.device;
struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
struct nv31_mpeg *mpeg = nv31_mpeg(engine);
struct nvkm_device *device = mpeg->engine.subdev.device;
nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch);
nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit);
......@@ -164,23 +163,24 @@ nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
static bool
nv31_mpeg_mthd(struct nv31_mpeg *mpeg, u32 mthd, u32 data)
{
struct nvkm_device *device = mpeg->base.engine.subdev.device;
struct nvkm_device *device = mpeg->engine.subdev.device;
switch (mthd) {
case 0x190:
case 0x1a0:
case 0x1b0:
return mpeg->mthd_dma(device, mthd, data);
return mpeg->func->mthd_dma(device, mthd, data);
default:
break;
}
return false;
}
void
nv31_mpeg_intr(struct nvkm_subdev *subdev)
static void
nv31_mpeg_intr(struct nvkm_engine *engine)
{
struct nv31_mpeg *mpeg = (void *)subdev;
struct nvkm_device *device = mpeg->base.engine.subdev.device;
struct nv31_mpeg *mpeg = nv31_mpeg(engine);
struct nvkm_subdev *subdev = &mpeg->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x00b100);
u32 type = nvkm_rd32(device, 0x00b230);
u32 mthd = nvkm_rd32(device, 0x00b234);
......@@ -188,7 +188,7 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
u32 show = stat;
unsigned long flags;
spin_lock_irqsave(&mpeg->base.engine.lock, flags);
spin_lock_irqsave(&mpeg->engine.lock, flags);
if (stat & 0x01000000) {
/* happens on initial binding of the object */
......@@ -213,61 +213,19 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
"unknown", stat, type, mthd, data);
}
spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
}
static const struct nvkm_engine_func
nv31_mpeg = {
.fifo.cclass = nv31_mpeg_chan_new,
.sclass = {
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
{}
}
};
static int
nv31_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv31_mpeg *mpeg;
int ret;
ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
*pobject = nv_object(mpeg);
if (ret)
return ret;
mpeg->base.engine.func = &nv31_mpeg;
mpeg->mthd_dma = nv31_mpeg_mthd_dma;
nv_subdev(mpeg)->unit = 0x00000002;
nv_subdev(mpeg)->intr = nv31_mpeg_intr;
nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
return 0;
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
}
int
nv31_mpeg_init(struct nvkm_object *object)
nv31_mpeg_init(struct nvkm_engine *mpeg)
{
struct nvkm_engine *engine = nv_engine(object);
struct nv31_mpeg *mpeg = (void *)object;
struct nvkm_subdev *subdev = &mpeg->base.engine.subdev;
struct nvkm_subdev *subdev = &mpeg->subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_fb *fb = device->fb;
int ret, i;
ret = nvkm_mpeg_init(&mpeg->base);
if (ret)
return ret;
/* VPE init */
nvkm_wr32(device, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
nvkm_wr32(device, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
for (i = 0; i < fb->tile.regions; i++)
engine->tile_prog(engine, i);
/* PMPEG init */
nvkm_wr32(device, 0x00b32c, 0x00000000);
nvkm_wr32(device, 0x00b314, 0x00000100);
......@@ -290,13 +248,47 @@ nv31_mpeg_init(struct nvkm_object *object)
return 0;
}
struct nvkm_oclass
nv31_mpeg_oclass = {
.handle = NV_ENGINE(MPEG, 0x31),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv31_mpeg_ctor,
.dtor = _nvkm_mpeg_dtor,
.init = nv31_mpeg_init,
.fini = _nvkm_mpeg_fini,
},
static void *
nv31_mpeg_dtor(struct nvkm_engine *engine)
{
return nv31_mpeg(engine);
}
static const struct nvkm_engine_func
nv31_mpeg_ = {
.dtor = nv31_mpeg_dtor,
.init = nv31_mpeg_init,
.intr = nv31_mpeg_intr,
.tile = nv31_mpeg_tile,
.fifo.cclass = nv31_mpeg_chan_new,
.sclass = {
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
{}
}
};
int
nv31_mpeg_new_(const struct nv31_mpeg_func *func, struct nvkm_device *device,
int index, struct nvkm_engine **pmpeg)
{
struct nv31_mpeg *mpeg;
if (!(mpeg = kzalloc(sizeof(*mpeg), GFP_KERNEL)))
return -ENOMEM;
mpeg->func = func;
*pmpeg = &mpeg->engine;
return nvkm_engine_ctor(&nv31_mpeg_, device, index, 0x00000002,
true, &mpeg->engine);
}
static const struct nv31_mpeg_func
nv31_mpeg = {
.mthd_dma = nv31_mpeg_mthd_dma,
};
int
nv31_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
{
return nv31_mpeg_new_(&nv31_mpeg, device, index, pmpeg);
}
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h
View file @ 7624fc01
#ifndef __NV31_MPEG_H__
#define __NV31_MPEG_H__
#define nv31_mpeg(p) container_of((p), struct nv31_mpeg, base.engine)
#define nv31_mpeg(p) container_of((p), struct nv31_mpeg, engine)
#include "priv.h"
#include <engine/mpeg.h>
struct nv31_mpeg {
struct nvkm_mpeg base;
const struct nv31_mpeg_func *func;
struct nvkm_engine engine;
struct nv31_mpeg_chan *chan;
};
int nv31_mpeg_new_(const struct nv31_mpeg_func *, struct nvkm_device *,
int index, struct nvkm_engine **);
struct nv31_mpeg_func {
bool (*mthd_dma)(struct nvkm_device *, u32 mthd, u32 data);
};
......
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
View file @ 7624fc01
......@@ -65,60 +65,13 @@ nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
return true;
}
static void
nv40_mpeg_intr(struct nvkm_subdev *subdev)
{
struct nv31_mpeg *mpeg = (void *)subdev;
struct nvkm_device *device = mpeg->base.engine.subdev.device;
u32 stat;
if ((stat = nvkm_rd32(device, 0x00b100)))
nv31_mpeg_intr(subdev);
if ((stat = nvkm_rd32(device, 0x00b800))) {
nvkm_error(subdev, "PMSRCH %08x\n", stat);
nvkm_wr32(device, 0x00b800, stat);
}
}
static const struct nvkm_engine_func
static const struct nv31_mpeg_func
nv40_mpeg = {
.fifo.cclass = nv31_mpeg_chan_new,
.sclass = {
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
{}
}
.mthd_dma = nv40_mpeg_mthd_dma,
};
static int
nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
int
nv40_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
{
struct nv31_mpeg *mpeg;
int ret;
ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
*pobject = nv_object(mpeg);
if (ret)
return ret;
mpeg->base.engine.func = &nv40_mpeg;
mpeg->mthd_dma = nv40_mpeg_mthd_dma;
nv_subdev(mpeg)->unit = 0x00000002;
nv_subdev(mpeg)->intr = nv40_mpeg_intr;
nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
return 0;
return nv31_mpeg_new_(&nv40_mpeg, device, index, pmpeg);
}
struct nvkm_oclass
nv40_mpeg_oclass = {
.handle = NV_ENGINE(MPEG, 0x40),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_mpeg_ctor,
.dtor = _nvkm_mpeg_dtor,
.init = nv31_mpeg_init,
.fini = _nvkm_mpeg_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
View file @ 7624fc01
......@@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#define nv44_mpeg(p) container_of((p), struct nv44_mpeg, base.engine)
#define nv44_mpeg(p) container_of((p), struct nv44_mpeg, engine)
#include "priv.h"
#include <core/client.h>
......@@ -31,12 +31,10 @@
#include <nvif/class.h>
struct nv44_mpeg {
struct nvkm_mpeg base;
struct nvkm_engine engine;
struct list_head chan;
};
bool nv40_mpeg_mthd_dma(struct nvkm_device *, u32, u32);
/*******************************************************************************
* PMPEG context
******************************************************************************/
......@@ -72,7 +70,7 @@ nv44_mpeg_chan_fini(struct nvkm_object *object, bool suspend)
struct nv44_mpeg_chan *chan = nv44_mpeg_chan(object);
struct nv44_mpeg *mpeg = chan->mpeg;
struct nvkm_device *device = mpeg->base.engine.subdev.device;
struct nvkm_device *device = mpeg->engine.subdev.device;
u32 inst = 0x80000000 | (chan->inst >> 4);
nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000000);
......@@ -88,9 +86,9 @@ nv44_mpeg_chan_dtor(struct nvkm_object *object)
struct nv44_mpeg_chan *chan = nv44_mpeg_chan(object);
struct nv44_mpeg *mpeg = chan->mpeg;
unsigned long flags;
spin_lock_irqsave(&mpeg->base.engine.lock, flags);
spin_lock_irqsave(&mpeg->engine.lock, flags);
list_del(&chan->head);
spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
return chan;
}
......@@ -117,9 +115,9 @@ nv44_mpeg_chan_new(struct nvkm_fifo_chan *fifoch,
chan->fifo = fifoch;
*pobject = &chan->object;
spin_lock_irqsave(&mpeg->base.engine.lock, flags);
spin_lock_irqsave(&mpeg->engine.lock, flags);
list_add(&chan->head, &mpeg->chan);
spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
return 0;
}
......@@ -142,11 +140,12 @@ nv44_mpeg_mthd(struct nvkm_device *device, u32 mthd, u32 data)
}
static void
nv44_mpeg_intr(struct nvkm_subdev *subdev)
nv44_mpeg_intr(struct nvkm_engine *engine)
{
struct nv44_mpeg *mpeg = (void *)subdev;
struct nv44_mpeg *mpeg = nv44_mpeg(engine);
struct nvkm_subdev *subdev = &mpeg->engine.subdev;
struct nvkm_device *device = subdev->device;
struct nv44_mpeg_chan *temp, *chan = NULL;
struct nvkm_device *device = mpeg->base.engine.subdev.device;
unsigned long flags;
u32 inst = nvkm_rd32(device, 0x00b318) & 0x000fffff;
u32 stat = nvkm_rd32(device, 0x00b100);
......@@ -155,7 +154,7 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
u32 data = nvkm_rd32(device, 0x00b238);
u32 show = stat;
spin_lock_irqsave(&mpeg->base.engine.lock, flags);
spin_lock_irqsave(&mpeg->engine.lock, flags);
list_for_each_entry(temp, &mpeg->chan, head) {
if (temp->inst >> 4 == inst) {
chan = temp;
......@@ -188,27 +187,14 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
stat, type, mthd, data);
}
spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
}
static void
nv44_mpeg_me_intr(struct nvkm_subdev *subdev)
{
struct nvkm_mpeg *mpeg = (void *)subdev;
struct nvkm_device *device = mpeg->engine.subdev.device;
u32 stat;
if ((stat = nvkm_rd32(device, 0x00b100)))
nv44_mpeg_intr(subdev);
if ((stat = nvkm_rd32(device, 0x00b800))) {
nvkm_error(subdev, "PMSRCH %08x\n", stat);
nvkm_wr32(device, 0x00b800, stat);
}
spin_unlock_irqrestore(&mpeg->engine.lock, flags);
}
static const struct nvkm_engine_func
nv44_mpeg = {
.init = nv31_mpeg_init,
.intr = nv44_mpeg_intr,
.tile = nv31_mpeg_tile,
.fifo.cclass = nv44_mpeg_chan_new,
.sclass = {
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
......@@ -216,35 +202,16 @@ nv44_mpeg = {
}
};
static int
nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
int
nv44_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
{
struct nv44_mpeg *mpeg;
int ret;
ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
*pobject = nv_object(mpeg);
if (ret)
return ret;
if (!(mpeg = kzalloc(sizeof(*mpeg), GFP_KERNEL)))
return -ENOMEM;
INIT_LIST_HEAD(&mpeg->chan);
mpeg->base.engine.func = &nv44_mpeg;
*pmpeg = &mpeg->engine;
nv_subdev(mpeg)->unit = 0x00000002;
nv_subdev(mpeg)->intr = nv44_mpeg_me_intr;
nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
return 0;
return nvkm_engine_ctor(&nv44_mpeg, device, index, 0x00000002,
true, &mpeg->engine);
}
struct nvkm_oclass
nv44_mpeg_oclass = {
.handle = NV_ENGINE(MPEG, 0x44),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv44_mpeg_ctor,
.dtor = _nvkm_mpeg_dtor,
.init = nv31_mpeg_init,
.fini = _nvkm_mpeg_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c
View file @ 7624fc01
......@@ -57,10 +57,10 @@ nv50_mpeg_cclass = {
******************************************************************************/
void
nv50_mpeg_intr(struct nvkm_subdev *subdev)
nv50_mpeg_intr(struct nvkm_engine *mpeg)
{
struct nvkm_mpeg *mpeg = (void *)subdev;
struct nvkm_device *device = mpeg->engine.subdev.device;
struct nvkm_subdev *subdev = &mpeg->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x00b100);
u32 type = nvkm_rd32(device, 0x00b230);
u32 mthd = nvkm_rd32(device, 0x00b234);
......@@ -84,61 +84,11 @@ nv50_mpeg_intr(struct nvkm_subdev *subdev)
nvkm_wr32(device, 0x00b230, 0x00000001);
}
static void
nv50_vpe_intr(struct nvkm_subdev *subdev)
{
struct nvkm_device *device = subdev->device;
if (nvkm_rd32(device, 0x00b100))
nv50_mpeg_intr(subdev);
if (nvkm_rd32(device, 0x00b800)) {
u32 stat = nvkm_rd32(device, 0x00b800);
nvkm_info(subdev, "PMSRCH: %08x\n", stat);
nvkm_wr32(device, 0xb800, stat);
}
}
static const struct nvkm_engine_func
nv50_mpeg = {
.cclass = &nv50_mpeg_cclass,
.sclass = {
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
{}
}
};
static int
nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_mpeg *mpeg;
int ret;
ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
*pobject = nv_object(mpeg);
if (ret)
return ret;
mpeg->engine.func = &nv50_mpeg;
nv_subdev(mpeg)->unit = 0x00400002;
nv_subdev(mpeg)->intr = nv50_vpe_intr;
return 0;
}
int
nv50_mpeg_init(struct nvkm_object *object)
nv50_mpeg_init(struct nvkm_engine *mpeg)
{
struct nvkm_mpeg *mpeg = (void *)object;
struct nvkm_subdev *subdev = &mpeg->engine.subdev;
struct nvkm_subdev *subdev = &mpeg->subdev;
struct nvkm_device *device = subdev->device;
int ret;
ret = nvkm_mpeg_init(mpeg);
if (ret)
return ret;
nvkm_wr32(device, 0x00b32c, 0x00000000);
nvkm_wr32(device, 0x00b314, 0x00000100);
......@@ -166,13 +116,20 @@ nv50_mpeg_init(struct nvkm_object *object)
return 0;
}
struct nvkm_oclass
nv50_mpeg_oclass = {
.handle = NV_ENGINE(MPEG, 0x50),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_mpeg_ctor,
.dtor = _nvkm_mpeg_dtor,
.init = nv50_mpeg_init,
.fini = _nvkm_mpeg_fini,
},
static const struct nvkm_engine_func
nv50_mpeg = {
.init = nv50_mpeg_init,
.intr = nv50_mpeg_intr,
.cclass = &nv50_mpeg_cclass,
.sclass = {
{ -1, -1, NV31_MPEG, &nv31_mpeg_object },
{}
}
};
int
nv50_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
{
return nvkm_engine_new_(&nv50_mpeg, device, index, 0x00400002,
true, pmpeg);
}
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/priv.h
View file @ 7624fc01
......@@ -3,7 +3,14 @@
#include <engine/mpeg.h>
struct nvkm_fifo_chan;
int nv31_mpeg_init(struct nvkm_engine *);
void nv31_mpeg_tile(struct nvkm_engine *, int, struct nvkm_fb_tile *);
extern const struct nvkm_object_func nv31_mpeg_object;
bool nv40_mpeg_mthd_dma(struct nvkm_device *, u32, u32);
int nv50_mpeg_init(struct nvkm_engine *);
void nv50_mpeg_intr(struct nvkm_engine *);
extern const struct nvkm_object_func nv50_mpeg_cclass;
#endif
drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c
View file @ 7624fc01
......@@ -56,8 +56,8 @@ nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile)
fb->func->tile.prog(fb, region, tile);
if (device->gr)
nvkm_engine_tile(&device->gr->engine, region);
if (likely(device->mpeg))
device->mpeg->tile_prog(device->mpeg, region);
if (device->mpeg)
nvkm_engine_tile(device->mpeg, region);
}
}
......
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