Skip to content

L
linux
Commit 7632b30e authored by Ben Skeggs's avatar Ben Skeggs
Browse files
Options

drm/nouveau/clk: namespace + nvidia gpu names (no binary change) 

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 5f8824de
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 613 additions and 613 deletions
drivers/gpu/drm/nouveau/include/nvkm/core/os.h
View file @ 7632b30e
......@@ -201,5 +201,23 @@
#define nouveau_bios_oclass nvkm_bios_oclass
#define nouveau_pll_vals nvkm_pll_vals
#define nouveau_therm_trip_point nvkm_therm_trip_point
#define nouveau_fb nvkm_fb
#define nouveau_fifo nvkm_fifo
#define nouveau_therm nvkm_therm
#define nouveau_therm_cstate nvkm_therm_cstate
#define nouveau_volt nvkm_volt
#define nouveau_timer nvkm_timer
#define nouveau_timer_wait_eq nvkm_timer_wait_eq
#define nva3_pll_calc gt215_pll_calc
#define nouveau_clk nvkm_clk
#define nouveau_domain nvkm_domain
#define nouveau_cstate nvkm_cstate
#define nouveau_pstate nvkm_pstate
#define nouveau_clk_astate nvkm_clk_astate
#define nouveau_clk_ustate nvkm_clk_ustate
#define nva3_clk_pre gt215_clk_pre
#define nva3_clk_post gt215_clk_post
#define nva3_clk_info gt215_clk_info
#define nva3_pll_info gt215_pll_info
#endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
View file @ 7632b30e
#ifndef __NOUVEAU_CLK_H__
#define __NOUVEAU_CLK_H__
#include <core/device.h>
#include <core/notify.h>
#ifndef __NVKM_CLK_H__
#define __NVKM_CLK_H__
#include <core/subdev.h>
struct nouveau_pll_vals;
#include <core/notify.h>
struct nvbios_pll;
struct nvkm_pll_vals;
enum nv_clk_src {
nv_clk_src_crystal,
......@@ -50,25 +47,34 @@ enum nv_clk_src {
nv_clk_src_max,
};
struct nouveau_cstate {
struct nvkm_cstate {
struct list_head head;
u8 voltage;
u32 domain[nv_clk_src_max];
};
struct nouveau_pstate {
struct nvkm_pstate {
struct list_head head;
struct list_head list; /* c-states */
struct nouveau_cstate base;
struct nvkm_cstate base;
u8 pstate;
u8 fanspeed;
};
struct nouveau_clk {
struct nouveau_subdev base;
struct nvkm_domain {
enum nv_clk_src name;
u8 bios; /* 0xff for none */
#define NVKM_CLK_DOM_FLAG_CORE 0x01
u8 flags;
const char *mname;
int mdiv;
};
struct nouveau_domain *domains;
struct nouveau_pstate bstate;
struct nvkm_clk {
struct nvkm_subdev base;
struct nvkm_domain *domains;
struct nvkm_pstate bstate;
struct list_head states;
int state_nr;
......@@ -88,80 +94,68 @@ struct nouveau_clk {
bool allow_reclock;
int (*read)(struct nouveau_clk *, enum nv_clk_src);
int (*calc)(struct nouveau_clk *, struct nouveau_cstate *);
int (*prog)(struct nouveau_clk *);
void (*tidy)(struct nouveau_clk *);
int (*read)(struct nvkm_clk *, enum nv_clk_src);
int (*calc)(struct nvkm_clk *, struct nvkm_cstate *);
int (*prog)(struct nvkm_clk *);
void (*tidy)(struct nvkm_clk *);
/*XXX: die, these are here *only* to support the completely
* bat-shit insane what-was-nouveau_hw.c code
* bat-shit insane what-was-nvkm_hw.c code
*/
int (*pll_calc)(struct nouveau_clk *, struct nvbios_pll *,
int clk, struct nouveau_pll_vals *pv);
int (*pll_prog)(struct nouveau_clk *, u32 reg1,
struct nouveau_pll_vals *pv);
int (*pll_calc)(struct nvkm_clk *, struct nvbios_pll *, int clk,
struct nvkm_pll_vals *pv);
int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv);
};
static inline struct nouveau_clk *
nouveau_clk(void *obj)
static inline struct nvkm_clk *
nvkm_clk(void *obj)
{
return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_CLK);
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_CLK);
}
struct nouveau_domain {
enum nv_clk_src name;
u8 bios; /* 0xff for none */
#define NVKM_CLK_DOM_FLAG_CORE 0x01
u8 flags;
const char *mname;
int mdiv;
};
#define nouveau_clk_create(p,e,o,i,r,s,n,d) \
nouveau_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \
#define nvkm_clk_create(p,e,o,i,r,s,n,d) \
nvkm_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \
(void **)d)
#define nouveau_clk_destroy(p) ({ \
struct nouveau_clk *clk = (p); \
_nouveau_clk_dtor(nv_object(clk)); \
#define nvkm_clk_destroy(p) ({ \
struct nvkm_clk *clk = (p); \
_nvkm_clk_dtor(nv_object(clk)); \
})
#define nouveau_clk_init(p) ({ \
struct nouveau_clk *clk = (p); \
_nouveau_clk_init(nv_object(clk)); \
#define nvkm_clk_init(p) ({ \
struct nvkm_clk *clk = (p); \
_nvkm_clk_init(nv_object(clk)); \
})
#define nouveau_clk_fini(p,s) ({ \
struct nouveau_clk *clk = (p); \
_nouveau_clk_fini(nv_object(clk), (s)); \
#define nvkm_clk_fini(p,s) ({ \
struct nvkm_clk *clk = (p); \
_nvkm_clk_fini(nv_object(clk), (s)); \
})
int nouveau_clk_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *,
struct nouveau_domain *, struct nouveau_pstate *,
int nvkm_clk_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *,
struct nvkm_domain *, struct nvkm_pstate *,
int, bool, int, void **);
void _nouveau_clk_dtor(struct nouveau_object *);
int _nouveau_clk_init(struct nouveau_object *);
int _nouveau_clk_fini(struct nouveau_object *, bool);
extern struct nouveau_oclass nv04_clk_oclass;
extern struct nouveau_oclass nv40_clk_oclass;
extern struct nouveau_oclass *nv50_clk_oclass;
extern struct nouveau_oclass *nv84_clk_oclass;
extern struct nouveau_oclass *nvaa_clk_oclass;
extern struct nouveau_oclass nva3_clk_oclass;
extern struct nouveau_oclass nvc0_clk_oclass;
extern struct nouveau_oclass nve0_clk_oclass;
extern struct nouveau_oclass gk20a_clk_oclass;
int nv04_clk_pll_set(struct nouveau_clk *, u32 type, u32 freq);
int nv04_clk_pll_calc(struct nouveau_clk *, struct nvbios_pll *,
int clk, struct nouveau_pll_vals *);
int nv04_clk_pll_prog(struct nouveau_clk *, u32 reg1,
struct nouveau_pll_vals *);
int nva3_clk_pll_calc(struct nouveau_clk *, struct nvbios_pll *,
int clk, struct nouveau_pll_vals *);
int nouveau_clk_ustate(struct nouveau_clk *, int req, int pwr);
int nouveau_clk_astate(struct nouveau_clk *, int req, int rel, bool wait);
int nouveau_clk_dstate(struct nouveau_clk *, int req, int rel);
int nouveau_clk_tstate(struct nouveau_clk *, int req, int rel);
void _nvkm_clk_dtor(struct nvkm_object *);
int _nvkm_clk_init(struct nvkm_object *);
int _nvkm_clk_fini(struct nvkm_object *, bool);
extern struct nvkm_oclass nv04_clk_oclass;
extern struct nvkm_oclass nv40_clk_oclass;
extern struct nvkm_oclass *nv50_clk_oclass;
extern struct nvkm_oclass *g84_clk_oclass;
extern struct nvkm_oclass *mcp77_clk_oclass;
extern struct nvkm_oclass gt215_clk_oclass;
extern struct nvkm_oclass gf100_clk_oclass;
extern struct nvkm_oclass gk104_clk_oclass;
extern struct nvkm_oclass gk20a_clk_oclass;
int nv04_clk_pll_set(struct nvkm_clk *, u32 type, u32 freq);
int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk,
struct nvkm_pll_vals *);
int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *);
int gt215_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *,
int clk, struct nvkm_pll_vals *);
int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr);
int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait);
int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel);
int nvkm_clk_tstate(struct nvkm_clk *, int req, int rel);
#endif
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View file @ 7632b30e
......@@ -65,7 +65,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
......@@ -107,7 +107,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
#if 0
/* looks to be some non-trivial changes */
device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
/* priv ring says no to 0x10eb14 writes */
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
#endif
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View file @ 7632b30e
......@@ -93,7 +93,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
......@@ -122,7 +122,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
......@@ -151,7 +151,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
......@@ -180,7 +180,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
......@@ -209,7 +209,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
......@@ -238,7 +238,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
......@@ -267,7 +267,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
......@@ -296,7 +296,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
......@@ -325,7 +325,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
......@@ -354,7 +354,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
......@@ -385,7 +385,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
......@@ -415,7 +415,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
......@@ -445,7 +445,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
View file @ 7632b30e
......@@ -65,7 +65,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -98,7 +98,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -131,7 +131,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -163,7 +163,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -196,7 +196,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -228,7 +228,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -260,7 +260,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -293,7 +293,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -325,7 +325,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
View file @ 7632b30e
......@@ -65,7 +65,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -99,7 +99,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -133,7 +133,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -189,7 +189,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -223,7 +223,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -257,7 +257,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......@@ -290,7 +290,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
......
drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
View file @ 7632b30e
......@@ -2,11 +2,11 @@ nvkm-y += nvkm/subdev/clk/base.o
nvkm-y += nvkm/subdev/clk/nv04.o
nvkm-y += nvkm/subdev/clk/nv40.o
nvkm-y += nvkm/subdev/clk/nv50.o
nvkm-y += nvkm/subdev/clk/nv84.o
nvkm-y += nvkm/subdev/clk/nva3.o
nvkm-y += nvkm/subdev/clk/nvaa.o
nvkm-y += nvkm/subdev/clk/nvc0.o
nvkm-y += nvkm/subdev/clk/nve0.o
nvkm-y += nvkm/subdev/clk/g84.o
nvkm-y += nvkm/subdev/clk/gt215.o
nvkm-y += nvkm/subdev/clk/mcp77.o
nvkm-y += nvkm/subdev/clk/gf100.o
nvkm-y += nvkm/subdev/clk/gk104.o
nvkm-y += nvkm/subdev/clk/gk20a.o
nvkm-y += nvkm/subdev/clk/pllnv04.o
nvkm-y += nvkm/subdev/clk/pllnva3.o
nvkm-y += nvkm/subdev/clk/pllgt215.o
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c → drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c
View file @ 7632b30e
......@@ -21,11 +21,10 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nv50.h"
static struct nouveau_domain
nv84_domains[] = {
static struct nvkm_domain
g84_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
......@@ -35,14 +34,14 @@ nv84_domains[] = {
{ nv_clk_src_max }
};
struct nouveau_oclass *
nv84_clk_oclass = &(struct nv50_clk_oclass) {
struct nvkm_oclass *
g84_clk_oclass = &(struct nv50_clk_oclass) {
.base.handle = NV_SUBDEV(CLK, 0x84),
.base.ofuncs = &(struct nouveau_ofuncs) {
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_clk_ctor,
.dtor = _nouveau_clk_dtor,
.init = _nouveau_clk_init,
.fini = _nouveau_clk_fini,
.dtor = _nvkm_clk_dtor,
.init = _nvkm_clk_init,
.fini = _nvkm_clk_fini,
},
.domains = nv84_domains,
.domains = g84_domains,
}.base;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c → drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
View file @ 7632b30e
......@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/clk.h>
#include "pll.h"
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
#include "pll.h"
struct nvc0_clk_info {
struct gf100_clk_info {
u32 freq;
u32 ssel;
u32 mdiv;
......@@ -38,17 +37,17 @@ struct nvc0_clk_info {
u32 coef;
};
struct nvc0_clk_priv {
struct nouveau_clk base;
struct nvc0_clk_info eng[16];
struct gf100_clk_priv {
struct nvkm_clk base;
struct gf100_clk_info eng[16];
};
static u32 read_div(struct nvc0_clk_priv *, int, u32, u32);
static u32 read_div(struct gf100_clk_priv *, int, u32, u32);
static u32
read_vco(struct nvc0_clk_priv *priv, u32 dsrc)
read_vco(struct gf100_clk_priv *priv, u32 dsrc)
{
struct nouveau_clk *clk = &priv->base;
struct nvkm_clk *clk = &priv->base;
u32 ssrc = nv_rd32(priv, dsrc);
if (!(ssrc & 0x00000100))
return clk->read(clk, nv_clk_src_sppll0);
......@@ -56,9 +55,9 @@ read_vco(struct nvc0_clk_priv *priv, u32 dsrc)
}
static u32
read_pll(struct nvc0_clk_priv *priv, u32 pll)
read_pll(struct gf100_clk_priv *priv, u32 pll)
{
struct nouveau_clk *clk = &priv->base;
struct nvkm_clk *clk = &priv->base;
u32 ctrl = nv_rd32(priv, pll + 0x00);
u32 coef = nv_rd32(priv, pll + 0x04);
u32 P = (coef & 0x003f0000) >> 16;
......@@ -95,7 +94,7 @@ read_pll(struct nvc0_clk_priv *priv, u32 pll)
}
static u32
read_div(struct nvc0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
read_div(struct gf100_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
{
u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
u32 sctl = nv_rd32(priv, dctl + (doff * 4));
......@@ -121,7 +120,7 @@ read_div(struct nvc0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
}
static u32
read_clk(struct nvc0_clk_priv *priv, int clk)
read_clk(struct gf100_clk_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
u32 ssel = nv_rd32(priv, 0x137100);
......@@ -145,10 +144,10 @@ read_clk(struct nvc0_clk_priv *priv, int clk)
}
static int
nvc0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
gf100_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
struct nouveau_device *device = nv_device(clk);
struct nvc0_clk_priv *priv = (void *)clk;
struct nvkm_device *device = nv_device(clk);
struct gf100_clk_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
......@@ -196,7 +195,7 @@ nvc0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
}
static u32
calc_div(struct nvc0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
calc_div(struct gf100_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
{
u32 div = min((ref * 2) / freq, (u32)65);
if (div < 2)
......@@ -207,7 +206,7 @@ calc_div(struct nvc0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
}
static u32
calc_src(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
calc_src(struct gf100_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
{
u32 sclk;
......@@ -236,9 +235,9 @@ calc_src(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
}
static u32
calc_pll(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *coef)
calc_pll(struct gf100_clk_priv *priv, int clk, u32 freq, u32 *coef)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pll limits;
int N, M, P, ret;
......@@ -250,7 +249,7 @@ calc_pll(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *coef)
if (!limits.refclk)
return 0;
ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
ret = gt215_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
if (ret <= 0)
return 0;
......@@ -259,10 +258,10 @@ calc_pll(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *coef)
}
static int
calc_clk(struct nvc0_clk_priv *priv,
struct nouveau_cstate *cstate, int clk, int dom)
calc_clk(struct gf100_clk_priv *priv,
struct nvkm_cstate *cstate, int clk, int dom)
{
struct nvc0_clk_info *info = &priv->eng[clk];
struct gf100_clk_info *info = &priv->eng[clk];
u32 freq = cstate->domain[dom];
u32 src0, div0, div1D, div1P = 0;
u32 clk0, clk1 = 0;
......@@ -311,9 +310,9 @@ calc_clk(struct nvc0_clk_priv *priv,
}
static int
nvc0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
gf100_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
struct nvc0_clk_priv *priv = (void *)clk;
struct gf100_clk_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
......@@ -330,9 +329,9 @@ nvc0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
}
static void
nvc0_clk_prog_0(struct nvc0_clk_priv *priv, int clk)
gf100_clk_prog_0(struct gf100_clk_priv *priv, int clk)
{
struct nvc0_clk_info *info = &priv->eng[clk];
struct gf100_clk_info *info = &priv->eng[clk];
if (clk < 7 && !info->ssel) {
nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
......@@ -340,16 +339,16 @@ nvc0_clk_prog_0(struct nvc0_clk_priv *priv, int clk)
}
static void
nvc0_clk_prog_1(struct nvc0_clk_priv *priv, int clk)
gf100_clk_prog_1(struct gf100_clk_priv *priv, int clk)
{
nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
}
static void
nvc0_clk_prog_2(struct nvc0_clk_priv *priv, int clk)
gf100_clk_prog_2(struct gf100_clk_priv *priv, int clk)
{
struct nvc0_clk_info *info = &priv->eng[clk];
struct gf100_clk_info *info = &priv->eng[clk];
const u32 addr = 0x137000 + (clk * 0x20);
if (clk <= 7) {
nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
......@@ -364,9 +363,9 @@ nvc0_clk_prog_2(struct nvc0_clk_priv *priv, int clk)
}
static void
nvc0_clk_prog_3(struct nvc0_clk_priv *priv, int clk)
gf100_clk_prog_3(struct gf100_clk_priv *priv, int clk)
{
struct nvc0_clk_info *info = &priv->eng[clk];
struct gf100_clk_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137100, (1 << clk), info->ssel);
nv_wait(priv, 0x137100, (1 << clk), info->ssel);
......@@ -374,24 +373,24 @@ nvc0_clk_prog_3(struct nvc0_clk_priv *priv, int clk)
}
static void
nvc0_clk_prog_4(struct nvc0_clk_priv *priv, int clk)
gf100_clk_prog_4(struct gf100_clk_priv *priv, int clk)
{
struct nvc0_clk_info *info = &priv->eng[clk];
struct gf100_clk_info *info = &priv->eng[clk];
nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
}
static int
nvc0_clk_prog(struct nouveau_clk *clk)
gf100_clk_prog(struct nvkm_clk *clk)
{
struct nvc0_clk_priv *priv = (void *)clk;
struct gf100_clk_priv *priv = (void *)clk;
struct {
void (*exec)(struct nvc0_clk_priv *, int);
void (*exec)(struct gf100_clk_priv *, int);
} stage[] = {
{ nvc0_clk_prog_0 }, /* div programming */
{ nvc0_clk_prog_1 }, /* select div mode */
{ nvc0_clk_prog_2 }, /* (maybe) program pll */
{ nvc0_clk_prog_3 }, /* (maybe) select pll mode */
{ nvc0_clk_prog_4 }, /* final divider */
{ gf100_clk_prog_0 }, /* div programming */
{ gf100_clk_prog_1 }, /* select div mode */
{ gf100_clk_prog_2 }, /* (maybe) program pll */
{ gf100_clk_prog_3 }, /* (maybe) select pll mode */
{ gf100_clk_prog_4 }, /* final divider */
};
int i, j;
......@@ -407,14 +406,14 @@ nvc0_clk_prog(struct nouveau_clk *clk)
}
static void
nvc0_clk_tidy(struct nouveau_clk *clk)
gf100_clk_tidy(struct nvkm_clk *clk)
{
struct nvc0_clk_priv *priv = (void *)clk;
struct gf100_clk_priv *priv = (void *)clk;
memset(priv->eng, 0x00, sizeof(priv->eng));
}
static struct nouveau_domain
nvc0_domain[] = {
static struct nvkm_domain
gf100_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_hubk06 , 0x00 },
......@@ -430,33 +429,33 @@ nvc0_domain[] = {
};
static int
nvc0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
gf100_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvc0_clk_priv *priv;
struct gf100_clk_priv *priv;
int ret;
ret = nouveau_clk_create(parent, engine, oclass, nvc0_domain, NULL, 0,
false, &priv);
ret = nvkm_clk_create(parent, engine, oclass, gf100_domain,
NULL, 0, false, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.read = nvc0_clk_read;
priv->base.calc = nvc0_clk_calc;
priv->base.prog = nvc0_clk_prog;
priv->base.tidy = nvc0_clk_tidy;
priv->base.read = gf100_clk_read;
priv->base.calc = gf100_clk_calc;
priv->base.prog = gf100_clk_prog;
priv->base.tidy = gf100_clk_tidy;
return 0;
}
struct nouveau_oclass
nvc0_clk_oclass = {
struct nvkm_oclass
gf100_clk_oclass = {
.handle = NV_SUBDEV(CLK, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_clk_ctor,
.dtor = _nouveau_clk_dtor,
.init = _nouveau_clk_init,
.fini = _nouveau_clk_fini,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_clk_ctor,
.dtor = _nvkm_clk_dtor,
.init = _nvkm_clk_init,
.fini = _nvkm_clk_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
View file @ 7632b30e
......@@ -22,6 +22,12 @@
* Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
*
*/
#include <subdev/clk.h>
#include <subdev/timer.h>
#ifdef __KERNEL__
#include <nouveau_platform.h>
#endif
#define MHZ (1000 * 1000)
......@@ -87,13 +93,6 @@
#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \
(0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)
#include <subdev/clk.h>
#include <subdev/timer.h>
#ifdef __KERNEL__
#include <nouveau_platform.h>
#endif
static const u8 pl_to_div[] = {
/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32,
......@@ -117,7 +116,7 @@ static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
};
struct gk20a_clk_priv {
struct nouveau_clk base;
struct nvkm_clk base;
const struct gk20a_clk_pllg_params *params;
u32 m, n, pl;
u32 parent_rate;
......@@ -260,7 +259,6 @@ gk20a_pllg_calc_mnp(struct gk20a_clk_priv *priv, unsigned long rate)
nv_debug(priv, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
target_freq, priv->m, priv->n, priv->pl, pl_to_div[priv->pl]);
return 0;
}
......@@ -402,8 +400,8 @@ _gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv, bool allow_slide)
nv_wr32(priv, GPCPLL_CFG, val);
}
if (!nouveau_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK,
GPCPLL_CFG_LOCK)) {
if (!nvkm_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK,
GPCPLL_CFG_LOCK)) {
nv_error(priv, "%s: timeout waiting for pllg lock\n", __func__);
return -ETIMEDOUT;
}
......@@ -458,14 +456,14 @@ gk20a_pllg_disable(struct gk20a_clk_priv *priv)
#define GK20A_CLK_GPC_MDIV 1000
static struct nouveau_domain
static struct nvkm_domain
gk20a_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
{ nv_clk_src_max }
};
static struct nouveau_pstate
static struct nvkm_pstate
gk20a_pstates[] = {
{
.base = {
......@@ -560,7 +558,7 @@ gk20a_pstates[] = {
};
static int
gk20a_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
gk20a_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
struct gk20a_clk_priv *priv = (void *)clk;
......@@ -577,7 +575,7 @@ gk20a_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
}
static int
gk20a_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
gk20a_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
struct gk20a_clk_priv *priv = (void *)clk;
......@@ -586,7 +584,7 @@ gk20a_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
}
static int
gk20a_clk_prog(struct nouveau_clk *clk)
gk20a_clk_prog(struct nvkm_clk *clk)
{
struct gk20a_clk_priv *priv = (void *)clk;
......@@ -594,17 +592,17 @@ gk20a_clk_prog(struct nouveau_clk *clk)
}
static void
gk20a_clk_tidy(struct nouveau_clk *clk)
gk20a_clk_tidy(struct nvkm_clk *clk)
{
}
static int
gk20a_clk_fini(struct nouveau_object *object, bool suspend)
gk20a_clk_fini(struct nvkm_object *object, bool suspend)
{
struct gk20a_clk_priv *priv = (void *)object;
int ret;
ret = nouveau_clk_fini(&priv->base, false);
ret = nvkm_clk_fini(&priv->base, false);
gk20a_pllg_disable(priv);
......@@ -612,14 +610,14 @@ gk20a_clk_fini(struct nouveau_object *object, bool suspend)
}
static int
gk20a_clk_init(struct nouveau_object *object)
gk20a_clk_init(struct nvkm_object *object)
{
struct gk20a_clk_priv *priv = (void *)object;
int ret;
nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);
ret = nouveau_clk_init(&priv->base);
ret = nvkm_clk_init(&priv->base);
if (ret)
return ret;
......@@ -633,9 +631,9 @@ gk20a_clk_init(struct nouveau_object *object)
}
static int
gk20a_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
gk20a_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct gk20a_clk_priv *priv;
struct nouveau_platform_device *plat;
......@@ -648,8 +646,9 @@ gk20a_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
gk20a_pstates[i].pstate = i + 1;
}
ret = nouveau_clk_create(parent, engine, oclass, gk20a_domains,
gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv);
ret = nvkm_clk_create(parent, engine, oclass, gk20a_domains,
gk20a_pstates, ARRAY_SIZE(gk20a_pstates),
true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
......@@ -664,16 +663,15 @@ gk20a_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.calc = gk20a_clk_calc;
priv->base.prog = gk20a_clk_prog;
priv->base.tidy = gk20a_clk_tidy;
return 0;
}
struct nouveau_oclass
struct nvkm_oclass
gk20a_clk_oclass = {
.handle = NV_SUBDEV(CLK, 0xea),
.ofuncs = &(struct nouveau_ofuncs) {
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_clk_ctor,
.dtor = _nouveau_subdev_dtor,
.dtor = _nvkm_subdev_dtor,
.init = gk20a_clk_init,
.fini = gk20a_clk_fini,
},
......
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h → drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h
View file @ 7632b30e
#ifndef __NVKM_CLK_NVA3_H__
#define __NVKM_CLK_NVA3_H__
#include <subdev/clk.h>
struct nva3_clk_info {
struct gt215_clk_info {
u32 clk;
u32 pll;
enum {
......@@ -13,8 +12,7 @@ struct nva3_clk_info {
u32 fb_delay;
};
int nva3_pll_info(struct nouveau_clk *, int, u32, u32,
struct nva3_clk_info *);
int nva3_clk_pre(struct nouveau_clk *clk, unsigned long *flags);
void nva3_clk_post(struct nouveau_clk *clk, unsigned long *flags);
int gt215_pll_info(struct nvkm_clk *, int, u32, u32, struct gt215_clk_info *);
int gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags);
void gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags);
#endif
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c → drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
View file @ 7632b30e
......@@ -21,18 +21,15 @@
*
* Authors: Ben Skeggs
*/
#include "gt215.h"
#include "pll.h"
#include <engine/fifo.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
#include <subdev/clk.h>
#include "nva3.h"
#include "pll.h"
struct nvaa_clk_priv {
struct nouveau_clk base;
struct mcp77_clk_priv {
struct nvkm_clk base;
enum nv_clk_src csrc, ssrc, vsrc;
u32 cctrl, sctrl;
u32 ccoef, scoef;
......@@ -41,13 +38,13 @@ struct nvaa_clk_priv {
};
static u32
read_div(struct nouveau_clk *clk)
read_div(struct nvkm_clk *clk)
{
return nv_rd32(clk, 0x004600);
}
static u32
read_pll(struct nouveau_clk *clk, u32 base)
read_pll(struct nvkm_clk *clk, u32 base)
{
u32 ctrl = nv_rd32(clk, base + 0);
u32 coef = nv_rd32(clk, base + 4);
......@@ -78,9 +75,9 @@ read_pll(struct nouveau_clk *clk, u32 base)
}
static int
nvaa_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
mcp77_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
struct nvaa_clk_priv *priv = (void *)clk;
struct mcp77_clk_priv *priv = (void *)clk;
u32 mast = nv_rd32(clk, 0x00c054);
u32 P = 0;
......@@ -160,12 +157,12 @@ nvaa_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
}
static u32
calc_pll(struct nvaa_clk_priv *priv, u32 reg,
calc_pll(struct mcp77_clk_priv *priv, u32 reg,
u32 clock, int *N, int *M, int *P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pll pll;
struct nouveau_clk *clk = &priv->base;
struct nvkm_clk *clk = &priv->base;
int ret;
ret = nvbios_pll_parse(bios, reg, &pll);
......@@ -199,9 +196,9 @@ calc_P(u32 src, u32 target, int *div)
}
static int
nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
mcp77_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
struct nvaa_clk_priv *priv = (void *)clk;
struct mcp77_clk_priv *priv = (void *)clk;
const int shader = cstate->domain[nv_clk_src_shader];
const int core = cstate->domain[nv_clk_src_core];
const int vdec = cstate->domain[nv_clk_src_vdec];
......@@ -216,8 +213,7 @@ nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
/* Calculate clock * 2, so shader clock can use it too */
clock = calc_pll(priv, 0x4028, (core << 1), &N, &M, &P1);
if (abs(core - out) <=
abs(core - (clock >> 1))) {
if (abs(core - out) <= abs(core - (clock >> 1))) {
priv->csrc = nv_clk_src_hclkm4;
priv->cctrl = divs << 16;
} else {
......@@ -242,9 +238,8 @@ nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
priv->ssrc = nv_clk_src_href;
} else {
clock = calc_pll(priv, 0x4020, shader, &N, &M, &P1);
if (priv->csrc == nv_clk_src_core) {
if (priv->csrc == nv_clk_src_core)
out = calc_P((core << 1), shader, &divs);
}
if (abs(shader - out) <=
abs(shader - clock) &&
......@@ -261,8 +256,7 @@ nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
/* vclk */
out = calc_P(core, vdec, &divs);
clock = calc_P(500000, vdec, &P1);
if(abs(vdec - out) <=
abs(vdec - clock)) {
if(abs(vdec - out) <= abs(vdec - clock)) {
priv->vsrc = nv_clk_src_cclk;
priv->vdiv = divs << 16;
} else {
......@@ -297,15 +291,15 @@ nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
}
static int
nvaa_clk_prog(struct nouveau_clk *clk)
mcp77_clk_prog(struct nvkm_clk *clk)
{
struct nvaa_clk_priv *priv = (void *)clk;
struct mcp77_clk_priv *priv = (void *)clk;
u32 pllmask = 0, mast;
unsigned long flags;
unsigned long *f = &flags;
int ret = 0;
ret = nva3_clk_pre(clk, f);
ret = gt215_clk_pre(clk, f);
if (ret)
goto out;
......@@ -382,18 +376,17 @@ nvaa_clk_prog(struct nouveau_clk *clk)
if (ret == -EBUSY)
f = NULL;
nva3_clk_post(clk, f);
gt215_clk_post(clk, f);
return ret;
}
static void
nvaa_clk_tidy(struct nouveau_clk *clk)
mcp77_clk_tidy(struct nvkm_clk *clk)
{
}
static struct nouveau_domain
nvaa_domains[] = {
static struct nvkm_domain
mcp77_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
......@@ -403,33 +396,33 @@ nvaa_domains[] = {
};
static int
nvaa_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
mcp77_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvaa_clk_priv *priv;
struct mcp77_clk_priv *priv;
int ret;
ret = nouveau_clk_create(parent, engine, oclass, nvaa_domains, NULL,
0, true, &priv);
ret = nvkm_clk_create(parent, engine, oclass, mcp77_domains,
NULL, 0, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
priv->base.read = nvaa_clk_read;
priv->base.calc = nvaa_clk_calc;
priv->base.prog = nvaa_clk_prog;
priv->base.tidy = nvaa_clk_tidy;
priv->base.read = mcp77_clk_read;
priv->base.calc = mcp77_clk_calc;
priv->base.prog = mcp77_clk_prog;
priv->base.tidy = mcp77_clk_tidy;
return 0;
}
struct nouveau_oclass *
nvaa_clk_oclass = &(struct nouveau_oclass) {
struct nvkm_oclass *
mcp77_clk_oclass = &(struct nvkm_oclass) {
.handle = NV_SUBDEV(CLK, 0xaa),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvaa_clk_ctor,
.dtor = _nouveau_clk_dtor,
.init = _nouveau_clk_init,
.fini = _nouveau_clk_fini,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = mcp77_clk_ctor,
.dtor = _nvkm_clk_dtor,
.init = _nvkm_clk_init,
.fini = _nvkm_clk_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
View file @ 7632b30e
......@@ -21,21 +21,20 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/clk.h>
#include "pll.h"
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/clk.h>
#include <subdev/devinit/nv04.h>
#include "pll.h"
struct nv04_clk_priv {
struct nouveau_clk base;
struct nvkm_clk base;
};
int
nv04_clk_pll_calc(struct nouveau_clk *clock, struct nvbios_pll *info,
int clk, struct nouveau_pll_vals *pv)
nv04_clk_pll_calc(struct nvkm_clk *clock, struct nvbios_pll *info,
int clk, struct nvkm_pll_vals *pv)
{
int N1, M1, N2, M2, P;
int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P);
......@@ -51,11 +50,10 @@ nv04_clk_pll_calc(struct nouveau_clk *clock, struct nvbios_pll *info,
}
int
nv04_clk_pll_prog(struct nouveau_clk *clk, u32 reg1,
struct nouveau_pll_vals *pv)
nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv)
{
struct nouveau_devinit *devinit = nouveau_devinit(clk);
int cv = nouveau_bios(clk)->version.chip;
struct nvkm_devinit *devinit = nvkm_devinit(clk);
int cv = nvkm_bios(clk)->version.chip;
if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
cv >= 0x40) {
......@@ -69,21 +67,21 @@ nv04_clk_pll_prog(struct nouveau_clk *clk, u32 reg1,
return 0;
}
static struct nouveau_domain
static struct nvkm_domain
nv04_domain[] = {
{ nv_clk_src_max }
};
static int
nv04_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv04_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv04_clk_priv *priv;
int ret;
ret = nouveau_clk_create(parent, engine, oclass, nv04_domain, NULL, 0,
false, &priv);
ret = nvkm_clk_create(parent, engine, oclass, nv04_domain,
NULL, 0, false, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
......@@ -93,13 +91,13 @@ nv04_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
struct nouveau_oclass
struct nvkm_oclass
nv04_clk_oclass = {
.handle = NV_SUBDEV(CLK, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_clk_ctor,
.dtor = _nouveau_clk_dtor,
.init = _nouveau_clk_init,
.fini = _nouveau_clk_fini,
.dtor = _nvkm_clk_dtor,
.init = _nvkm_clk_init,
.fini = _nvkm_clk_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
View file @ 7632b30e
......@@ -21,22 +21,22 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/clk.h>
#include "pll.h"
#include <core/device.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
struct nv40_clk_priv {
struct nouveau_clk base;
struct nvkm_clk base;
u32 ctrl;
u32 npll_ctrl;
u32 npll_coef;
u32 spll;
};
static struct nouveau_domain
static struct nvkm_domain
nv40_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
......@@ -102,7 +102,7 @@ read_clk(struct nv40_clk_priv *priv, u32 src)
}
static int
nv40_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
nv40_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
struct nv40_clk_priv *priv = (void *)clk;
u32 mast = nv_rd32(priv, 0x00c040);
......@@ -128,9 +128,9 @@ nv40_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
static int
nv40_clk_calc_pll(struct nv40_clk_priv *priv, u32 reg, u32 clk,
int *N1, int *M1, int *N2, int *M2, int *log2P)
int *N1, int *M1, int *N2, int *M2, int *log2P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pll pll;
int ret;
......@@ -144,11 +144,12 @@ nv40_clk_calc_pll(struct nv40_clk_priv *priv, u32 reg, u32 clk,
ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P);
if (ret == 0)
return -ERANGE;
return ret;
}
static int
nv40_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
nv40_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
struct nv40_clk_priv *priv = (void *)clk;
int gclk = cstate->domain[nv_clk_src_core];
......@@ -158,7 +159,7 @@ nv40_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
/* core/geometric clock */
ret = nv40_clk_calc_pll(priv, 0x004000, gclk,
&N1, &M1, &N2, &M2, &log2P);
&N1, &M1, &N2, &M2, &log2P);
if (ret < 0)
return ret;
......@@ -173,7 +174,7 @@ nv40_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
/* use the second pll for shader/rop clock, if it differs from core */
if (sclk && sclk != gclk) {
ret = nv40_clk_calc_pll(priv, 0x004008, sclk,
&N1, &M1, NULL, NULL, &log2P);
&N1, &M1, NULL, NULL, &log2P);
if (ret < 0)
return ret;
......@@ -188,7 +189,7 @@ nv40_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
}
static int
nv40_clk_prog(struct nouveau_clk *clk)
nv40_clk_prog(struct nvkm_clk *clk)
{
struct nv40_clk_priv *priv = (void *)clk;
nv_mask(priv, 0x00c040, 0x00000333, 0x00000000);
......@@ -201,20 +202,20 @@ nv40_clk_prog(struct nouveau_clk *clk)
}
static void
nv40_clk_tidy(struct nouveau_clk *clk)
nv40_clk_tidy(struct nvkm_clk *clk)
{
}
static int
nv40_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv40_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv40_clk_priv *priv;
int ret;
ret = nouveau_clk_create(parent, engine, oclass, nv40_domain, NULL, 0,
true, &priv);
ret = nvkm_clk_create(parent, engine, oclass, nv40_domain,
NULL, 0, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
......@@ -228,13 +229,13 @@ nv40_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
struct nouveau_oclass
struct nvkm_oclass
nv40_clk_oclass = {
.handle = NV_SUBDEV(CLK, 0x40),
.ofuncs = &(struct nouveau_ofuncs) {
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_clk_ctor,
.dtor = _nouveau_clk_dtor,
.init = _nouveau_clk_init,
.fini = _nouveau_clk_fini,
.dtor = _nvkm_clk_dtor,
.init = _nvkm_clk_init,
.fini = _nvkm_clk_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
View file @ 7632b30e
......@@ -21,14 +21,14 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "nv50.h"
#include "pll.h"
#include "seq.h"
#include <core/device.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
static u32
read_div(struct nv50_clk_priv *priv)
{
......@@ -51,7 +51,7 @@ read_div(struct nv50_clk_priv *priv)
static u32
read_pll_src(struct nv50_clk_priv *priv, u32 base)
{
struct nouveau_clk *clk = &priv->base;
struct nvkm_clk *clk = &priv->base;
u32 coef, ref = clk->read(clk, nv_clk_src_crystal);
u32 rsel = nv_rd32(priv, 0x00e18c);
int P, N, M, id;
......@@ -116,13 +116,14 @@ read_pll_src(struct nv50_clk_priv *priv, u32 base)
if (M)
return (ref * N / M) >> P;
return 0;
}
static u32
read_pll_ref(struct nv50_clk_priv *priv, u32 base)
{
struct nouveau_clk *clk = &priv->base;
struct nvkm_clk *clk = &priv->base;
u32 src, mast = nv_rd32(priv, 0x00c040);
switch (base) {
......@@ -147,13 +148,14 @@ read_pll_ref(struct nv50_clk_priv *priv, u32 base)
if (src)
return clk->read(clk, nv_clk_src_href);
return read_pll_src(priv, base);
}
static u32
read_pll(struct nv50_clk_priv *priv, u32 base)
{
struct nouveau_clk *clk = &priv->base;
struct nvkm_clk *clk = &priv->base;
u32 mast = nv_rd32(priv, 0x00c040);
u32 ctrl = nv_rd32(priv, base + 0);
u32 coef = nv_rd32(priv, base + 4);
......@@ -162,7 +164,7 @@ read_pll(struct nv50_clk_priv *priv, u32 base)
int N1, N2, M1, M2;
if (base == 0x004028 && (mast & 0x00100000)) {
/* wtf, appears to only disable post-divider on nva0 */
/* wtf, appears to only disable post-divider on gt200 */
if (nv_device(priv)->chipset != 0xa0)
return clk->read(clk, nv_clk_src_dom6);
}
......@@ -185,7 +187,7 @@ read_pll(struct nv50_clk_priv *priv, u32 base)
}
static int
nv50_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
nv50_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
{
struct nv50_clk_priv *priv = (void *)clk;
u32 mast = nv_rd32(priv, 0x00c040);
......@@ -318,7 +320,7 @@ nv50_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
static u32
calc_pll(struct nv50_clk_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_pll pll;
int ret;
......@@ -359,7 +361,7 @@ clk_same(u32 a, u32 b)
}
static int
nv50_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
nv50_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
{
struct nv50_clk_priv *priv = (void *)clk;
struct nv50_clk_hwsq *hwsq = &priv->hwsq;
......@@ -484,30 +486,30 @@ nv50_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
}
static int
nv50_clk_prog(struct nouveau_clk *clk)
nv50_clk_prog(struct nvkm_clk *clk)
{
struct nv50_clk_priv *priv = (void *)clk;
return clk_exec(&priv->hwsq, true);
}
static void
nv50_clk_tidy(struct nouveau_clk *clk)
nv50_clk_tidy(struct nvkm_clk *clk)
{
struct nv50_clk_priv *priv = (void *)clk;
clk_exec(&priv->hwsq, false);
}
int
nv50_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv50_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv50_clk_oclass *pclass = (void *)oclass;
struct nv50_clk_priv *priv;
int ret;
ret = nouveau_clk_create(parent, engine, oclass, pclass->domains,
NULL, 0, false, &priv);
ret = nvkm_clk_create(parent, engine, oclass, pclass->domains,
NULL, 0, false, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
......@@ -536,7 +538,7 @@ nv50_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
static struct nouveau_domain
static struct nvkm_domain
nv50_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
......@@ -546,14 +548,14 @@ nv50_domains[] = {
{ nv_clk_src_max }
};
struct nouveau_oclass *
struct nvkm_oclass *
nv50_clk_oclass = &(struct nv50_clk_oclass) {
.base.handle = NV_SUBDEV(CLK, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_clk_ctor,
.dtor = _nouveau_clk_dtor,
.init = _nouveau_clk_init,
.fini = _nouveau_clk_fini,
.dtor = _nvkm_clk_dtor,
.init = _nvkm_clk_init,
.fini = _nvkm_clk_fini,
},
.domains = nv50_domains,
}.base;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
View file @ 7632b30e
#ifndef __NVKM_CLK_NV50_H__
#define __NVKM_CLK_NV50_H__
#include <subdev/bus.h>
#include <subdev/bus/hwsq.h>
#include <subdev/clk.h>
......@@ -15,17 +13,16 @@ struct nv50_clk_hwsq {
};
struct nv50_clk_priv {
struct nouveau_clk base;
struct nvkm_clk base;
struct nv50_clk_hwsq hwsq;
};
int nv50_clk_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
int nv50_clk_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
struct nv50_clk_oclass {
struct nouveau_oclass base;
struct nouveau_domain *domains;
struct nvkm_oclass base;
struct nvkm_domain *domains;
};
#endif
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h
View file @ 7632b30e
#ifndef __NOUVEAU_PLL_H__
#define __NOUVEAU_PLL_H__
#ifndef __NVKM_PLL_H__
#define __NVKM_PLL_H__
#include <core/os.h>
struct nvkm_subdev;
struct nvbios_pll;
int nv04_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq,
int nv04_pll_calc(struct nvkm_subdev *, struct nvbios_pll *, u32 freq,
int *N1, int *M1, int *N2, int *M2, int *P);
int nva3_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq,
int gt215_pll_calc(struct nvkm_subdev *, struct nvbios_pll *, u32 freq,
int *N, int *fN, int *M, int *P);
#endif
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c → drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.c
View file @ 7632b30e
......@@ -21,16 +21,14 @@
*
* Authors: Ben Skeggs
*/
#include "pll.h"
#include <subdev/clk.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
int
nva3_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info,
u32 freq, int *pN, int *pfN, int *pM, int *P)
gt215_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info,
u32 freq, int *pN, int *pfN, int *pM, int *P)
{
u32 best_err = ~0, err;
int M, lM, hM, N, fN;
......
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
View file @ 7632b30e
......@@ -20,14 +20,13 @@
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "pll.h"
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
static int
getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
getMNP_single(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk,
int *pN, int *pM, int *pP)
{
/* Find M, N and P for a single stage PLL
......@@ -38,7 +37,7 @@ getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
* "clk" parameter in kHz
* returns calculated clock
*/
struct nouveau_bios *bios = nouveau_bios(subdev);
struct nvkm_bios *bios = nvkm_bios(subdev);
int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq;
int minM = info->vco1.min_m, maxM = info->vco1.max_m;
int minN = info->vco1.min_n, maxN = info->vco1.max_n;
......@@ -126,7 +125,7 @@ getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
}
static int
getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
getMNP_double(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk,
int *pN1, int *pM1, int *pN2, int *pM2, int *pP)
{
/* Find M, N and P for a two stage PLL
......@@ -137,7 +136,7 @@ getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
* "clk" parameter in kHz
* returns calculated clock
*/
int chip_version = nouveau_bios(subdev)->version.chip;
int chip_version = nvkm_bios(subdev)->version.chip;
int minvco1 = info->vco1.min_freq, maxvco1 = info->vco1.max_freq;
int minvco2 = info->vco2.min_freq, maxvco2 = info->vco2.max_freq;
int minU1 = info->vco1.min_inputfreq, minU2 = info->vco2.min_inputfreq;
......@@ -225,7 +224,7 @@ getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
}
int
nv04_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, u32 freq,
nv04_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info, u32 freq,
int *N1, int *M1, int *N2, int *M2, int *P)
{
int ret;
......
drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h
View file @ 7632b30e
#ifndef __NVKM_CLK_SEQ_H__
#define __NVKM_CLK_SEQ_H__
#include <subdev/bus.h>
#include <subdev/bus/hwsq.h>
#define clk_init(s,p) hwsq_init(&(s)->base, (p))
......@@ -13,5 +11,4 @@
#define clk_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d))
#define clk_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d))
#define clk_nsec(s,n) hwsq_nsec(&(s)->base, (n))
#endif
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
View file @ 7632b30e
......@@ -30,7 +30,7 @@
#include <subdev/bios/M0205.h>
#include <subdev/bios/timing.h>
#include <subdev/clk/nva3.h>
#include <subdev/clk/gt215.h>
#include <subdev/clk/pll.h>
#include <subdev/gpio.h>
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7