Commit 7664a1fd authored by Vikas Chaudhary's avatar Vikas Chaudhary Committed by James Bottomley

[SCSI] qla4xxx: Update structure and variable names

Signed-off-by: default avatarVikas Chaudhary <vikas.chaudhary@qlogic.com>
Reviewed-by: default avatarMike Christie <michaelc@cs.wisc.edu>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent f8086f4f
...@@ -37,7 +37,7 @@ void qla4xxx_dump_registers(struct scsi_qla_host *ha) ...@@ -37,7 +37,7 @@ void qla4xxx_dump_registers(struct scsi_qla_host *ha)
if (is_qla8022(ha)) { if (is_qla8022(ha)) {
for (i = 1; i < MBOX_REG_COUNT; i++) for (i = 1; i < MBOX_REG_COUNT; i++)
printk(KERN_INFO "mailbox[%d] = 0x%08X\n", printk(KERN_INFO "mailbox[%d] = 0x%08X\n",
i, readl(&ha->qla4_8xxx_reg->mailbox_in[i])); i, readl(&ha->qla4_82xx_reg->mailbox_in[i]));
return; return;
} }
......
...@@ -647,7 +647,7 @@ struct scsi_qla_host { ...@@ -647,7 +647,7 @@ struct scsi_qla_host {
uint8_t acb_version; uint8_t acb_version;
/* qla82xx specific fields */ /* qla82xx specific fields */
struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */ struct device_reg_82xx __iomem *qla4_82xx_reg; /* Base I/O address */
unsigned long nx_pcibase; /* Base I/O address */ unsigned long nx_pcibase; /* Base I/O address */
uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */ uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
unsigned long nx_db_wr_ptr; /* Door bell write pointer */ unsigned long nx_db_wr_ptr; /* Door bell write pointer */
......
...@@ -102,11 +102,11 @@ int qla4xxx_init_rings(struct scsi_qla_host *ha) ...@@ -102,11 +102,11 @@ int qla4xxx_init_rings(struct scsi_qla_host *ha)
if (is_qla8022(ha)) { if (is_qla8022(ha)) {
writel(0, writel(0,
(unsigned long __iomem *)&ha->qla4_8xxx_reg->req_q_out); (unsigned long __iomem *)&ha->qla4_82xx_reg->req_q_out);
writel(0, writel(0,
(unsigned long __iomem *)&ha->qla4_8xxx_reg->rsp_q_in); (unsigned long __iomem *)&ha->qla4_82xx_reg->rsp_q_in);
writel(0, writel(0,
(unsigned long __iomem *)&ha->qla4_8xxx_reg->rsp_q_out); (unsigned long __iomem *)&ha->qla4_82xx_reg->rsp_q_out);
} else { } else {
/* /*
* Initialize DMA Shadow registers. The firmware is really * Initialize DMA Shadow registers. The firmware is really
......
...@@ -219,8 +219,8 @@ void qla4_82xx_queue_iocb(struct scsi_qla_host *ha) ...@@ -219,8 +219,8 @@ void qla4_82xx_queue_iocb(struct scsi_qla_host *ha)
**/ **/
void qla4_82xx_complete_iocb(struct scsi_qla_host *ha) void qla4_82xx_complete_iocb(struct scsi_qla_host *ha)
{ {
writel(ha->response_out, &ha->qla4_8xxx_reg->rsp_q_out); writel(ha->response_out, &ha->qla4_82xx_reg->rsp_q_out);
readl(&ha->qla4_8xxx_reg->rsp_q_out); readl(&ha->qla4_82xx_reg->rsp_q_out);
} }
/** /**
......
...@@ -607,7 +607,7 @@ static void qla4xxx_isr_decode_mailbox(struct scsi_qla_host * ha, ...@@ -607,7 +607,7 @@ static void qla4xxx_isr_decode_mailbox(struct scsi_qla_host * ha,
*/ */
for (i = 0; i < ha->mbox_status_count; i++) for (i = 0; i < ha->mbox_status_count; i++)
ha->mbox_status[i] = is_qla8022(ha) ha->mbox_status[i] = is_qla8022(ha)
? readl(&ha->qla4_8xxx_reg->mailbox_out[i]) ? readl(&ha->qla4_82xx_reg->mailbox_out[i])
: readl(&ha->reg->mailbox[i]); : readl(&ha->reg->mailbox[i]);
set_bit(AF_MBOX_COMMAND_DONE, &ha->flags); set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
...@@ -618,7 +618,7 @@ static void qla4xxx_isr_decode_mailbox(struct scsi_qla_host * ha, ...@@ -618,7 +618,7 @@ static void qla4xxx_isr_decode_mailbox(struct scsi_qla_host * ha,
} else if (mbox_status >> 12 == MBOX_ASYNC_EVENT_STATUS) { } else if (mbox_status >> 12 == MBOX_ASYNC_EVENT_STATUS) {
for (i = 0; i < MBOX_AEN_REG_COUNT; i++) for (i = 0; i < MBOX_AEN_REG_COUNT; i++)
mbox_sts[i] = is_qla8022(ha) mbox_sts[i] = is_qla8022(ha)
? readl(&ha->qla4_8xxx_reg->mailbox_out[i]) ? readl(&ha->qla4_82xx_reg->mailbox_out[i])
: readl(&ha->reg->mailbox[i]); : readl(&ha->reg->mailbox[i]);
/* Immediately process the AENs that don't require much work. /* Immediately process the AENs that don't require much work.
...@@ -832,11 +832,11 @@ void qla4_82xx_interrupt_service_routine(struct scsi_qla_host *ha, ...@@ -832,11 +832,11 @@ void qla4_82xx_interrupt_service_routine(struct scsi_qla_host *ha,
/* Process mailbox/asynch event interrupt.*/ /* Process mailbox/asynch event interrupt.*/
if (intr_status & HSRX_RISC_MB_INT) if (intr_status & HSRX_RISC_MB_INT)
qla4xxx_isr_decode_mailbox(ha, qla4xxx_isr_decode_mailbox(ha,
readl(&ha->qla4_8xxx_reg->mailbox_out[0])); readl(&ha->qla4_82xx_reg->mailbox_out[0]));
/* clear the interrupt */ /* clear the interrupt */
writel(0, &ha->qla4_8xxx_reg->host_int); writel(0, &ha->qla4_82xx_reg->host_int);
readl(&ha->qla4_8xxx_reg->host_int); readl(&ha->qla4_82xx_reg->host_int);
} }
/** /**
...@@ -879,7 +879,7 @@ static void qla4_82xx_spurious_interrupt(struct scsi_qla_host *ha, ...@@ -879,7 +879,7 @@ static void qla4_82xx_spurious_interrupt(struct scsi_qla_host *ha,
DEBUG2(ql4_printk(KERN_INFO, ha, "Spurious Interrupt\n")); DEBUG2(ql4_printk(KERN_INFO, ha, "Spurious Interrupt\n"));
if (is_qla8022(ha)) { if (is_qla8022(ha)) {
writel(0, &ha->qla4_8xxx_reg->host_int); writel(0, &ha->qla4_82xx_reg->host_int);
if (test_bit(AF_INTx_ENABLED, &ha->flags)) if (test_bit(AF_INTx_ENABLED, &ha->flags))
qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
0xfbff); 0xfbff);
...@@ -1020,12 +1020,12 @@ irqreturn_t qla4_82xx_intr_handler(int irq, void *dev_id) ...@@ -1020,12 +1020,12 @@ irqreturn_t qla4_82xx_intr_handler(int irq, void *dev_id)
spin_lock_irqsave(&ha->hardware_lock, flags); spin_lock_irqsave(&ha->hardware_lock, flags);
while (1) { while (1) {
if (!(readl(&ha->qla4_8xxx_reg->host_int) & if (!(readl(&ha->qla4_82xx_reg->host_int) &
ISRX_82XX_RISC_INT)) { ISRX_82XX_RISC_INT)) {
qla4_82xx_spurious_interrupt(ha, reqs_count); qla4_82xx_spurious_interrupt(ha, reqs_count);
break; break;
} }
intr_status = readl(&ha->qla4_8xxx_reg->host_status); intr_status = readl(&ha->qla4_82xx_reg->host_status);
if ((intr_status & if ((intr_status &
(HSRX_RISC_MB_INT | HSRX_RISC_IOCB_INT)) == 0) { (HSRX_RISC_MB_INT | HSRX_RISC_IOCB_INT)) == 0) {
qla4_82xx_spurious_interrupt(ha, reqs_count); qla4_82xx_spurious_interrupt(ha, reqs_count);
...@@ -1086,13 +1086,13 @@ qla4_8xxx_default_intr_handler(int irq, void *dev_id) ...@@ -1086,13 +1086,13 @@ qla4_8xxx_default_intr_handler(int irq, void *dev_id)
spin_lock_irqsave(&ha->hardware_lock, flags); spin_lock_irqsave(&ha->hardware_lock, flags);
while (1) { while (1) {
if (!(readl(&ha->qla4_8xxx_reg->host_int) & if (!(readl(&ha->qla4_82xx_reg->host_int) &
ISRX_82XX_RISC_INT)) { ISRX_82XX_RISC_INT)) {
qla4_82xx_spurious_interrupt(ha, reqs_count); qla4_82xx_spurious_interrupt(ha, reqs_count);
break; break;
} }
intr_status = readl(&ha->qla4_8xxx_reg->host_status); intr_status = readl(&ha->qla4_82xx_reg->host_status);
if ((intr_status & if ((intr_status &
(HSRX_RISC_MB_INT | HSRX_RISC_IOCB_INT)) == 0) { (HSRX_RISC_MB_INT | HSRX_RISC_IOCB_INT)) == 0) {
qla4_82xx_spurious_interrupt(ha, reqs_count); qla4_82xx_spurious_interrupt(ha, reqs_count);
...@@ -1118,7 +1118,7 @@ qla4_8xxx_msix_rsp_q(int irq, void *dev_id) ...@@ -1118,7 +1118,7 @@ qla4_8xxx_msix_rsp_q(int irq, void *dev_id)
spin_lock_irqsave(&ha->hardware_lock, flags); spin_lock_irqsave(&ha->hardware_lock, flags);
qla4xxx_process_response_queue(ha); qla4xxx_process_response_queue(ha);
writel(0, &ha->qla4_8xxx_reg->host_int); writel(0, &ha->qla4_82xx_reg->host_int);
spin_unlock_irqrestore(&ha->hardware_lock, flags); spin_unlock_irqrestore(&ha->hardware_lock, flags);
ha->isr_count++; ha->isr_count++;
......
...@@ -111,10 +111,10 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount, ...@@ -111,10 +111,10 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
printk("\n")); printk("\n"));
for (i = 1; i < inCount; i++) for (i = 1; i < inCount; i++)
writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]); writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]); writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
readl(&ha->qla4_8xxx_reg->mailbox_in[0]); readl(&ha->qla4_82xx_reg->mailbox_in[0]);
writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint); writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
} else { } else {
/* Load all mailbox registers, except mailbox 0. */ /* Load all mailbox registers, except mailbox 0. */
for (i = 1; i < inCount; i++) for (i = 1; i < inCount; i++)
...@@ -169,11 +169,11 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount, ...@@ -169,11 +169,11 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
spin_lock_irqsave(&ha->hardware_lock, flags); spin_lock_irqsave(&ha->hardware_lock, flags);
if (is_qla8022(ha)) { if (is_qla8022(ha)) {
intr_status = intr_status =
readl(&ha->qla4_8xxx_reg->host_int); readl(&ha->qla4_82xx_reg->host_int);
if (intr_status & ISRX_82XX_RISC_INT) { if (intr_status & ISRX_82XX_RISC_INT) {
ha->mbox_status_count = outCount; ha->mbox_status_count = outCount;
intr_status = intr_status =
readl(&ha->qla4_8xxx_reg->host_status); readl(&ha->qla4_82xx_reg->host_status);
ha->isp_ops->interrupt_service_routine( ha->isp_ops->interrupt_service_routine(
ha, intr_status); ha, intr_status);
if (test_bit(AF_INTERRUPTS_ON, if (test_bit(AF_INTERRUPTS_ON,
......
This diff is collapsed.
...@@ -835,7 +835,7 @@ struct crb_addr_pair { ...@@ -835,7 +835,7 @@ struct crb_addr_pair {
/* Driver_code is for driver to write some info about the entry /* Driver_code is for driver to write some info about the entry
* currently not used. * currently not used.
*/ */
struct qla82xx_minidump_entry_hdr { struct qla8xxx_minidump_entry_hdr {
uint32_t entry_type; uint32_t entry_type;
uint32_t entry_size; uint32_t entry_size;
uint32_t entry_capture_size; uint32_t entry_capture_size;
...@@ -848,8 +848,8 @@ struct qla82xx_minidump_entry_hdr { ...@@ -848,8 +848,8 @@ struct qla82xx_minidump_entry_hdr {
}; };
/* Read CRB entry header */ /* Read CRB entry header */
struct qla82xx_minidump_entry_crb { struct qla8xxx_minidump_entry_crb {
struct qla82xx_minidump_entry_hdr h; struct qla8xxx_minidump_entry_hdr h;
uint32_t addr; uint32_t addr;
struct { struct {
uint8_t addr_stride; uint8_t addr_stride;
...@@ -871,8 +871,8 @@ struct qla82xx_minidump_entry_crb { ...@@ -871,8 +871,8 @@ struct qla82xx_minidump_entry_crb {
uint32_t value_3; uint32_t value_3;
}; };
struct qla82xx_minidump_entry_cache { struct qla8xxx_minidump_entry_cache {
struct qla82xx_minidump_entry_hdr h; struct qla8xxx_minidump_entry_hdr h;
uint32_t tag_reg_addr; uint32_t tag_reg_addr;
struct { struct {
uint16_t tag_value_stride; uint16_t tag_value_stride;
...@@ -895,8 +895,8 @@ struct qla82xx_minidump_entry_cache { ...@@ -895,8 +895,8 @@ struct qla82xx_minidump_entry_cache {
}; };
/* Read OCM */ /* Read OCM */
struct qla82xx_minidump_entry_rdocm { struct qla8xxx_minidump_entry_rdocm {
struct qla82xx_minidump_entry_hdr h; struct qla8xxx_minidump_entry_hdr h;
uint32_t rsvd_0; uint32_t rsvd_0;
uint32_t rsvd_1; uint32_t rsvd_1;
uint32_t data_size; uint32_t data_size;
...@@ -908,24 +908,24 @@ struct qla82xx_minidump_entry_rdocm { ...@@ -908,24 +908,24 @@ struct qla82xx_minidump_entry_rdocm {
}; };
/* Read Memory */ /* Read Memory */
struct qla82xx_minidump_entry_rdmem { struct qla8xxx_minidump_entry_rdmem {
struct qla82xx_minidump_entry_hdr h; struct qla8xxx_minidump_entry_hdr h;
uint32_t rsvd[6]; uint32_t rsvd[6];
uint32_t read_addr; uint32_t read_addr;
uint32_t read_data_size; uint32_t read_data_size;
}; };
/* Read ROM */ /* Read ROM */
struct qla82xx_minidump_entry_rdrom { struct qla8xxx_minidump_entry_rdrom {
struct qla82xx_minidump_entry_hdr h; struct qla8xxx_minidump_entry_hdr h;
uint32_t rsvd[6]; uint32_t rsvd[6];
uint32_t read_addr; uint32_t read_addr;
uint32_t read_data_size; uint32_t read_data_size;
}; };
/* Mux entry */ /* Mux entry */
struct qla82xx_minidump_entry_mux { struct qla8xxx_minidump_entry_mux {
struct qla82xx_minidump_entry_hdr h; struct qla8xxx_minidump_entry_hdr h;
uint32_t select_addr; uint32_t select_addr;
uint32_t rsvd_0; uint32_t rsvd_0;
uint32_t data_size; uint32_t data_size;
...@@ -937,8 +937,8 @@ struct qla82xx_minidump_entry_mux { ...@@ -937,8 +937,8 @@ struct qla82xx_minidump_entry_mux {
}; };
/* Queue entry */ /* Queue entry */
struct qla82xx_minidump_entry_queue { struct qla8xxx_minidump_entry_queue {
struct qla82xx_minidump_entry_hdr h; struct qla8xxx_minidump_entry_hdr h;
uint32_t select_addr; uint32_t select_addr;
struct { struct {
uint16_t queue_id_stride; uint16_t queue_id_stride;
......
...@@ -3492,8 +3492,8 @@ static void qla4xxx_free_adapter(struct scsi_qla_host *ha) ...@@ -3492,8 +3492,8 @@ static void qla4xxx_free_adapter(struct scsi_qla_host *ha)
&ha->reg->ctrl_status); &ha->reg->ctrl_status);
readl(&ha->reg->ctrl_status); readl(&ha->reg->ctrl_status);
} else if (is_qla8022(ha)) { } else if (is_qla8022(ha)) {
writel(0, &ha->qla4_8xxx_reg->host_int); writel(0, &ha->qla4_82xx_reg->host_int);
readl(&ha->qla4_8xxx_reg->host_int); readl(&ha->qla4_82xx_reg->host_int);
} }
/* Remove timer thread, if present */ /* Remove timer thread, if present */
...@@ -3561,7 +3561,7 @@ int qla4_8xxx_iospace_config(struct scsi_qla_host *ha) ...@@ -3561,7 +3561,7 @@ int qla4_8xxx_iospace_config(struct scsi_qla_host *ha)
/* Mapping of IO base pointer, door bell read and write pointer */ /* Mapping of IO base pointer, door bell read and write pointer */
/* mapping of IO base pointer */ /* mapping of IO base pointer */
ha->qla4_8xxx_reg = ha->qla4_82xx_reg =
(struct device_reg_82xx __iomem *)((uint8_t *)ha->nx_pcibase + (struct device_reg_82xx __iomem *)((uint8_t *)ha->nx_pcibase +
0xbc000 + (ha->pdev->devfn << 11)); 0xbc000 + (ha->pdev->devfn << 11));
...@@ -3660,7 +3660,7 @@ static struct isp_operations qla4xxx_isp_ops = { ...@@ -3660,7 +3660,7 @@ static struct isp_operations qla4xxx_isp_ops = {
.get_sys_info = qla4xxx_get_sys_info, .get_sys_info = qla4xxx_get_sys_info,
}; };
static struct isp_operations qla4_8xxx_isp_ops = { static struct isp_operations qla4_82xx_isp_ops = {
.iospace_config = qla4_8xxx_iospace_config, .iospace_config = qla4_8xxx_iospace_config,
.pci_config = qla4_8xxx_pci_config, .pci_config = qla4_8xxx_pci_config,
.disable_intrs = qla4_82xx_disable_intrs, .disable_intrs = qla4_82xx_disable_intrs,
...@@ -3684,7 +3684,7 @@ uint16_t qla4xxx_rd_shdw_req_q_out(struct scsi_qla_host *ha) ...@@ -3684,7 +3684,7 @@ uint16_t qla4xxx_rd_shdw_req_q_out(struct scsi_qla_host *ha)
uint16_t qla4_82xx_rd_shdw_req_q_out(struct scsi_qla_host *ha) uint16_t qla4_82xx_rd_shdw_req_q_out(struct scsi_qla_host *ha)
{ {
return (uint16_t)le32_to_cpu(readl(&ha->qla4_8xxx_reg->req_q_out)); return (uint16_t)le32_to_cpu(readl(&ha->qla4_82xx_reg->req_q_out));
} }
uint16_t qla4xxx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha) uint16_t qla4xxx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha)
...@@ -3694,7 +3694,7 @@ uint16_t qla4xxx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha) ...@@ -3694,7 +3694,7 @@ uint16_t qla4xxx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha)
uint16_t qla4_82xx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha) uint16_t qla4_82xx_rd_shdw_rsp_q_in(struct scsi_qla_host *ha)
{ {
return (uint16_t)le32_to_cpu(readl(&ha->qla4_8xxx_reg->rsp_q_in)); return (uint16_t)le32_to_cpu(readl(&ha->qla4_82xx_reg->rsp_q_in));
} }
static ssize_t qla4xxx_show_boot_eth_info(void *data, int type, char *buf) static ssize_t qla4xxx_show_boot_eth_info(void *data, int type, char *buf)
...@@ -5074,7 +5074,7 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev, ...@@ -5074,7 +5074,7 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev,
/* Setup Runtime configurable options */ /* Setup Runtime configurable options */
if (is_qla8022(ha)) { if (is_qla8022(ha)) {
ha->isp_ops = &qla4_8xxx_isp_ops; ha->isp_ops = &qla4_82xx_isp_ops;
rwlock_init(&ha->hw_lock); rwlock_init(&ha->hw_lock);
ha->qdr_sn_window = -1; ha->qdr_sn_window = -1;
ha->ddr_mn_window = -1; ha->ddr_mn_window = -1;
......
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