ppc32: Update register definitions for Apple chipsets

parent 6b14a7b9
......@@ -18,6 +18,13 @@
#define KEYLARGO_FCR4 0x48
#define KEYLARGO_FCR5 0x4c /* Pangea only */
/* K2 aditional FCRs */
#define K2_FCR6 0x34
#define K2_FCR7 0x30
#define K2_FCR8 0x2c
#define K2_FCR9 0x28
#define K2_FCR10 0x24
/* GPIO registers */
#define KEYLARGO_GPIO_LEVELS0 0x50
#define KEYLARGO_GPIO_LEVELS1 0x54
......@@ -30,6 +37,10 @@
#define KEYLARGO_GPIO_OUTOUT_DATA 0x01
#define KEYLARGO_GPIO_INPUT_DATA 0x02
/* K2 does only extint GPIOs and does 51 of them */
#define K2_GPIO_EXTINT_0 0x58
#define K2_GPIO_EXTINT_CNT 51
/* Specific GPIO regs */
#define KL_GPIO_MODEM_RESET (KEYLARGO_GPIO_0+0x03)
......@@ -67,7 +78,8 @@
#define KL_GPIO_AIRPORT_4 (KEYLARGO_GPIO_0+0x0f)
/*
* Bits in feature control register
* Bits in feature control register. Those bits different for K2 are
* listed separately
*/
#define KL_MBCR_MB0_PCI_ENABLE 0x00000800 /* exist ? */
#define KL_MBCR_MB0_IDE_ENABLE 0x00001000
......@@ -202,9 +214,30 @@
#define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3))
/* Pangea and Intrepid only */
#define KL5_VIA_USE_CLK31 0x000000001 /* Pangea Only */
#define KL5_SCC_USE_CLK31 0x000000002 /* Pangea Only */
#define KL5_PWM_CLK32_EN 0x000000004
#define KL5_CLK3_68_EN 0x000000010
#define KL5_CLK32_EN 0x000000020
#define KL5_VIA_USE_CLK31 0000000001 /* Pangea Only */
#define KL5_SCC_USE_CLK31 0x00000002 /* Pangea Only */
#define KL5_PWM_CLK32_EN 0x00000004
#define KL5_CLK3_68_EN 0x00000010
#define KL5_CLK32_EN 0x00000020
/* K2 definitions */
#define K2_FCR0_USB0_SWRESET 0x00200000
#define K2_FCR0_USB1_SWRESET 0x02000000
#define K2_FCR0_RING_PME_DISABLE 0x08000000
#define K2_FCR1_PCI1_BUS_RESET_N 0x00000010
#define K2_FCR1_PCI1_SLEEP_RESET_EN 0x00000020
#define K2_FCR1_PCI1_CLK_ENABLE 0x00004000
#define K2_FCR1_FW_CLK_ENABLE 0x00008000
#define K2_FCR1_FW_RESET_N 0x00010000
#define K2_FCR1_GMAC_CLK_ENABLE 0x00400000
#define K2_FCR1_GMAC_POWER_DOWN 0x00800000
#define K2_FCR1_GMAC_RESET_N 0x01000000
#define K2_FCR1_SATA_CLK_ENABLE 0x02000000
#define K2_FCR1_SATA_POWER_DOWN 0x04000000
#define K2_FCR1_SATA_RESET_N 0x08000000
#define K2_FCR1_UATA_CLK_ENABLE 0x10000000
#define K2_FCR1_UATA_RESET_N 0x40000000
#define K2_FCR1_UATA_CHOOSE_CLK66 0x80000000
/*
* uninorth.h: definitions for using the "UniNorth" host bridge chip
* from Apple. This chip is used on "Core99" machines
* This also includes U2 used on more recent MacRISC2/3
* machines and U3 (G5)
*
*/
#ifdef __KERNEL__
......@@ -8,23 +10,26 @@
#define __ASM_UNINORTH_H__
/*
* Uni-N config space reg. definitions
* Uni-N and U3 config space reg. definitions
*
* (Little endian)
*/
/* Address ranges selection. This one should work with Bandit too */
/* Not U3 */
#define UNI_N_ADDR_SELECT 0x48
#define UNI_N_ADDR_COARSE_MASK 0xffff0000 /* 256Mb regions at *0000000 */
#define UNI_N_ADDR_FINE_MASK 0x0000ffff /* 16Mb regions at f*000000 */
/* AGP registers */
/* Not U3 */
#define UNI_N_CFG_GART_BASE 0x8c
#define UNI_N_CFG_AGP_BASE 0x90
#define UNI_N_CFG_GART_CTRL 0x94
#define UNI_N_CFG_INTERNAL_STATUS 0x98
/* UNI_N_CFG_GART_CTRL bits definitions */
/* Not U3 */
#define UNI_N_CFG_GART_INVAL 0x00000001
#define UNI_N_CFG_GART_ENABLE 0x00000100
#define UNI_N_CFG_GART_2xRESET 0x00010000
......@@ -90,6 +95,14 @@
/* Version of the UniNorth chip */
#define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */
#define UNI_N_VERSION_107 0x0003 /* 1.0.7 */
#define UNI_N_VERSION_10A 0x0007 /* 1.0.10 */
#define UNI_N_VERSION_150 0x0011 /* 1.5 */
#define UNI_N_VERSION_200 0x0024 /* 2.0 */
#define UNI_N_VERSION_PANGEA 0x00C0 /* Integrated U1 + K */
#define UNI_N_VERSION_INTREPID 0x00D2 /* Integrated U2 + K */
#define UNI_N_VERSION_300 0x0030 /* 3.0 (U3 on G5) */
/* This register is used to enable/disable various clocks */
#define UNI_N_CLOCK_CNTL 0x0020
#define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */
......@@ -131,5 +144,26 @@
/* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
/*
* U3 specific registers
*/
/* U3 Toggle */
#define U3_TOGGLE_REG 0x00e0
#define U3_PMC_START_STOP 0x0001
#define U3_MPIC_RESET 0x0002
#define U3_MPIC_OUTPUT_ENABLE 0x0004
/* U3 API PHY Config 1 */
#define U3_API_PHY_CONFIG_1 0x23030
/* U3 HyperTransport registers */
#define U3_HT_CONFIG_BASE 0x70000
#define U3_HT_LINK_COMMAND 0x100
#define U3_HT_LINK_CONFIG 0x110
#define U3_HT_LINK_FREQ 0x120
#endif /* __ASM_UNINORTH_H__ */
#endif /* __KERNEL__ */
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