Commit 7700b02a authored by Kai Germaschewski's avatar Kai Germaschewski

ISDN/HiSax: Un-inline hscx_irq.c

Each driver for HSCX based cards defined some hardware access macros
and #include'd hscx_irq.c. Instead, we now add the needed routines to
the corresponding bc_hw_ops and use regular function calls. It's a slight
bit less efficient, but shouldn't be noticable.
parent ef551c7e
......@@ -183,23 +183,6 @@ static struct bc_hw_ops hscx_ops = {
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs, \
cs->hw.asus.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, \
cs->hw.asus.hscx, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs, \
cs->hw.asus.hscx, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs, \
cs->hw.asus.hscx, (nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
static void
asuscom_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......
......@@ -113,17 +113,6 @@ static struct bc_hw_ops hscx_ops = {
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs->hw.avm.hscx[nr], reg)
#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.avm.hscx[nr], reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.avm.hscxfifo[nr], ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.avm.hscxfifo[nr], ptr, cnt)
#include "hscx_irq.c"
static void
avm_a1_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......
......@@ -168,17 +168,6 @@ static struct bc_hw_ops hscx_ops = {
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) hscx_read(cs, nr, reg)
#define WRITEHSCX(cs, nr, reg, data) hscx_write(cs, nr, reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) hscx_read_fifo(cs, nr, ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) hscx_write_fifo(cs, nr, ptr, cnt)
#include "hscx_irq.c"
static void
avm_a1p_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......
......@@ -160,21 +160,6 @@ set_ipac_active(struct IsdnCardState *cs, u_int active)
writereg(cs, IPAC_MASK, active ? 0xc0 : 0xff);
}
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs, \
reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, \
reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs, \
(nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs, \
(nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
static void
bkm_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs)
{
......
......@@ -339,23 +339,6 @@ static struct bc_hw_ops ipacx_bc_ops = {
.write_reg = ipacx_bc_write,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs->hw.diva.hscx_adr, \
cs->hw.diva.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \
cs->hw.diva.hscx, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.diva.hscx_adr, \
cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.diva.hscx_adr, \
cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
static void
diva_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......
......@@ -317,22 +317,6 @@ TimerRun(struct IsdnCardState *cs)
return (v & ELSA_TIMER_RUN_PCC8);
return (v & ELSA_TIMER_RUN);
}
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs, \
cs->hw.elsa.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, \
cs->hw.elsa.hscx, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs, \
cs->hw.elsa.hscx, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs, \
cs->hw.elsa.hscx, (nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
static void
elsa_interrupt(int intno, void *dev_id, struct pt_regs *regs)
......
......@@ -252,17 +252,6 @@ static struct bc_hw_ops hscx_ops = {
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) hscx_read(cs, nr, reg)
#define WRITEHSCX(cs, nr, reg, data) hscx_write(cs, nr, reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) hscx_read_fifo(cs, nr, ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) hscx_write_fifo(cs, nr, ptr, cnt)
#include "hscx_irq.c"
static void
gazel_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......
......@@ -22,7 +22,7 @@ static char *HSCXVer[] __initdata =
"?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"};
static inline u8
hscx_read_reg(struct BCState *bcs, u8 addr)
hscx_read(struct BCState *bcs, u8 addr)
{
struct IsdnCardState *cs = bcs->cs;
u8 hscx = bcs->hw.hscx.hscx;
......@@ -31,7 +31,7 @@ hscx_read_reg(struct BCState *bcs, u8 addr)
}
static inline void
hscx_write_reg(struct BCState *bcs, u8 addr, u8 val)
hscx_write(struct BCState *bcs, u8 addr, u8 val)
{
struct IsdnCardState *cs = bcs->cs;
u8 hscx = bcs->hw.hscx.hscx;
......@@ -39,6 +39,24 @@ hscx_write_reg(struct BCState *bcs, u8 addr, u8 val)
cs->bc_hw_ops->write_reg(cs, hscx, addr, val);
}
static inline void
hscx_read_fifo(struct BCState *bcs, u8 *p, int len)
{
struct IsdnCardState *cs = bcs->cs;
u8 hscx = bcs->hw.hscx.hscx;
cs->bc_hw_ops->read_fifo(cs, hscx, p, len);
}
static inline void
hscx_write_fifo(struct BCState *bcs, u8 *p, int len)
{
struct IsdnCardState *cs = bcs->cs;
u8 hscx = bcs->hw.hscx.hscx;
cs->bc_hw_ops->write_fifo(cs, hscx, p, len);
}
int __init
HscxVersion(struct IsdnCardState *cs, char *s)
{
......@@ -65,49 +83,49 @@ modehscx(struct BCState *bcs, int mode, int bc)
'A' + hscx, mode, bc);
bcs->mode = mode;
bcs->channel = bc;
hscx_write_reg(bcs, HSCX_XAD1, 0xFF);
hscx_write_reg(bcs, HSCX_XAD2, 0xFF);
hscx_write_reg(bcs, HSCX_RAH2, 0xFF);
hscx_write_reg(bcs, HSCX_XBCH, 0x0);
hscx_write_reg(bcs, HSCX_RLCR, 0x0);
hscx_write_reg(bcs, HSCX_CCR1,
hscx_write(bcs, HSCX_XAD1, 0xFF);
hscx_write(bcs, HSCX_XAD2, 0xFF);
hscx_write(bcs, HSCX_RAH2, 0xFF);
hscx_write(bcs, HSCX_XBCH, 0x0);
hscx_write(bcs, HSCX_RLCR, 0x0);
hscx_write(bcs, HSCX_CCR1,
test_bit(HW_IPAC, &cs->HW_Flags) ? 0x82 : 0x85);
hscx_write_reg(bcs, HSCX_CCR2, 0x30);
hscx_write_reg(bcs, HSCX_XCCR, 7);
hscx_write_reg(bcs, HSCX_RCCR, 7);
hscx_write(bcs, HSCX_CCR2, 0x30);
hscx_write(bcs, HSCX_XCCR, 7);
hscx_write(bcs, HSCX_RCCR, 7);
/* Switch IOM 1 SSI */
if (test_bit(HW_IOM1, &cs->HW_Flags) && (hscx == 0))
bc = 1 - bc;
if (bc == 0) {
hscx_write_reg(bcs, HSCX_TSAX,
hscx_write(bcs, HSCX_TSAX,
test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0);
hscx_write_reg(bcs, HSCX_TSAR,
hscx_write(bcs, HSCX_TSAR,
test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0);
} else {
hscx_write_reg(bcs, HSCX_TSAX, bcs->hw.hscx.tsaxr1);
hscx_write_reg(bcs, HSCX_TSAR, bcs->hw.hscx.tsaxr1);
hscx_write(bcs, HSCX_TSAX, bcs->hw.hscx.tsaxr1);
hscx_write(bcs, HSCX_TSAR, bcs->hw.hscx.tsaxr1);
}
switch (mode) {
case L1_MODE_NULL:
hscx_write_reg(bcs, HSCX_TSAX, 0x1f);
hscx_write_reg(bcs, HSCX_TSAR, 0x1f);
hscx_write_reg(bcs, HSCX_MODE, 0x84);
hscx_write(bcs, HSCX_TSAX, 0x1f);
hscx_write(bcs, HSCX_TSAR, 0x1f);
hscx_write(bcs, HSCX_MODE, 0x84);
break;
case L1_MODE_TRANS:
hscx_write_reg(bcs, HSCX_MODE, 0xe4);
hscx_write(bcs, HSCX_MODE, 0xe4);
break;
case L1_MODE_HDLC:
hscx_write_reg(bcs, HSCX_CCR1,
hscx_write(bcs, HSCX_CCR1,
test_bit(HW_IPAC, &cs->HW_Flags) ? 0x8a : 0x8d);
hscx_write_reg(bcs, HSCX_MODE, 0x8c);
hscx_write(bcs, HSCX_MODE, 0x8c);
break;
}
if (mode)
hscx_write_reg(bcs, HSCX_CMDR, 0x41);
hscx_write(bcs, HSCX_CMDR, 0x41);
hscx_write_reg(bcs, HSCX_ISTA, 0x00);
hscx_write(bcs, HSCX_ISTA, 0x00);
}
void
......@@ -226,32 +244,32 @@ inithscx(struct IsdnCardState *cs)
cs->bcs[1].hw.hscx.tsaxr0 = 0x2f;
cs->bcs[1].hw.hscx.tsaxr1 = 3;
val = hscx_read_reg(&cs->bcs[1], HSCX_ISTA);
val = hscx_read(&cs->bcs[1], HSCX_ISTA);
debugl1(cs, "HSCX B ISTA %x", val);
if (val & 0x01) {
eval = hscx_read_reg(&cs->bcs[1], HSCX_EXIR);
eval = hscx_read(&cs->bcs[1], HSCX_EXIR);
debugl1(cs, "HSCX B EXIR %x", eval);
}
if (val & 0x02) {
eval = hscx_read_reg(&cs->bcs[0], HSCX_EXIR);
eval = hscx_read(&cs->bcs[0], HSCX_EXIR);
debugl1(cs, "HSCX A EXIR %x", eval);
}
val = hscx_read_reg(&cs->bcs[0], HSCX_ISTA);
val = hscx_read(&cs->bcs[0], HSCX_ISTA);
debugl1(cs, "HSCX A ISTA %x", val);
val = hscx_read_reg(&cs->bcs[1], HSCX_STAR);
val = hscx_read(&cs->bcs[1], HSCX_STAR);
debugl1(cs, "HSCX B STAR %x", val);
val = hscx_read_reg(&cs->bcs[0], HSCX_STAR);
val = hscx_read(&cs->bcs[0], HSCX_STAR);
debugl1(cs, "HSCX A STAR %x", val);
/* disable all IRQ */
hscx_write_reg(&cs->bcs[0], HSCX_MASK, 0xFF);
hscx_write_reg(&cs->bcs[1], HSCX_MASK, 0xFF);
hscx_write(&cs->bcs[0], HSCX_MASK, 0xFF);
hscx_write(&cs->bcs[1], HSCX_MASK, 0xFF);
modehscx(&cs->bcs[0], 0, 0);
modehscx(&cs->bcs[1], 0, 0);
/* Reenable all IRQ */
hscx_write_reg(&cs->bcs[0], HSCX_MASK, 0x0);
hscx_write_reg(&cs->bcs[1], HSCX_MASK, 0x0);
hscx_write(&cs->bcs[0], HSCX_MASK, 0x0);
hscx_write(&cs->bcs[1], HSCX_MASK, 0x0);
}
void __init
......@@ -260,3 +278,5 @@ inithscxisac(struct IsdnCardState *cs)
initisac(cs);
inithscx(cs);
}
#include "hscx_irq.c"
......@@ -37,3 +37,5 @@
extern int HscxVersion(struct IsdnCardState *cs, char *s);
extern void modehscx(struct BCState *bcs, int mode, int bc);
extern void inithscxisac(struct IsdnCardState *cs);
extern void hscx_int_main(struct IsdnCardState *cs, u8 val);
extern void hscx_fill_fifo(struct BCState *bcs);
......@@ -12,13 +12,12 @@
*
*/
static inline void
waitforCEC(struct IsdnCardState *cs, int hscx)
static void
waitforCEC(struct BCState *bcs)
{
int to = 50;
while ((READHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) {
while ((hscx_read(bcs, HSCX_STAR) & 0x04) && to) {
udelay(1);
to--;
}
......@@ -28,11 +27,11 @@ waitforCEC(struct IsdnCardState *cs, int hscx)
static inline void
waitforXFW(struct IsdnCardState *cs, int hscx)
waitforXFW(struct BCState *bcs)
{
int to = 50;
while ((!(READHSCX(cs, hscx, HSCX_STAR) & 0x44) == 0x40) && to) {
while ((!(hscx_read(bcs, HSCX_STAR) & 0x44) == 0x40) && to) {
udelay(1);
to--;
}
......@@ -41,10 +40,10 @@ waitforXFW(struct IsdnCardState *cs, int hscx)
}
static inline void
hscx_writeCMDR(struct IsdnCardState *cs, int hscx, u8 data)
WriteHSCXCMDR(struct BCState *bcs, u8 data)
{
waitforCEC(cs, hscx);
WRITEHSCX(cs, hscx, HSCX_CMDR, data);
waitforCEC(bcs);
hscx_write(bcs, HSCX_CMDR, data);
}
......@@ -60,14 +59,14 @@ hscx_empty_fifo(struct BCState *bcs, int count)
if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "hscx_empty_fifo: incoming packet too large");
hscx_writeCMDR(cs, bcs->hw.hscx.hscx, 0x80);
WriteHSCXCMDR(bcs, 0x80);
bcs->hw.hscx.rcvidx = 0;
return;
}
ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
bcs->hw.hscx.rcvidx += count;
READHSCXFIFO(cs, bcs->hw.hscx.hscx, ptr, count);
hscx_writeCMDR(cs, bcs->hw.hscx.hscx, 0x80);
hscx_read_fifo(bcs, ptr, count);
WriteHSCXCMDR(bcs, 0x80);
if (cs->debug & L1_DEB_HSCX_FIFO) {
char *t = bcs->blog;
......@@ -78,7 +77,7 @@ hscx_empty_fifo(struct BCState *bcs, int count)
}
}
static void
void
hscx_fill_fifo(struct BCState *bcs)
{
struct IsdnCardState *cs = bcs->cs;
......@@ -101,13 +100,13 @@ hscx_fill_fifo(struct BCState *bcs)
} else
count = bcs->tx_skb->len;
waitforXFW(cs, bcs->hw.hscx.hscx);
waitforXFW(bcs);
ptr = bcs->tx_skb->data;
skb_pull(bcs->tx_skb, count);
bcs->tx_cnt -= count;
bcs->count += count;
WRITEHSCXFIFO(cs, bcs->hw.hscx.hscx, ptr, count);
hscx_writeCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa);
hscx_write_fifo(bcs, ptr, count);
WriteHSCXCMDR(bcs, more ? 0x8 : 0xa);
if (cs->debug & L1_DEB_HSCX_FIFO) {
char *t = bcs->blog;
......@@ -131,7 +130,7 @@ hscx_interrupt(struct IsdnCardState *cs, u8 val, u8 hscx)
return;
if (val & 0x80) { /* RME */
r = READHSCX(cs, hscx, HSCX_RSTA);
r = hscx_read(bcs, HSCX_RSTA);
if ((r & 0xf0) != 0xa0) {
if (!(r & 0x80)) {
if (cs->debug & L1_DEB_WARN)
......@@ -155,9 +154,9 @@ hscx_interrupt(struct IsdnCardState *cs, u8 val, u8 hscx)
bcs->err_crc++;
#endif
}
hscx_writeCMDR(cs, hscx, 0x80);
WriteHSCXCMDR(bcs, 0x80);
} else {
count = READHSCX(cs, hscx, HSCX_RBCL) & (
count = hscx_read(bcs, HSCX_RBCL) & (
test_bit(HW_IPAC, &cs->HW_Flags)? 0x3f: 0x1f);
if (count == 0)
count = fifo_size;
......@@ -198,10 +197,10 @@ hscx_interrupt(struct IsdnCardState *cs, u8 val, u8 hscx)
static void
reset_xmit(struct BCState *bcs)
{
hscx_writeCMDR(bcs->cs, bcs->hw.hscx.hscx, 0x01);
WriteHSCXCMDR(bcs, 0x01);
}
static inline void
void
hscx_int_main(struct IsdnCardState *cs, u8 val)
{
......@@ -211,7 +210,7 @@ hscx_int_main(struct IsdnCardState *cs, u8 val)
spin_lock(&cs->lock);
if (val & 0x01) {
bcs = cs->bcs + 1;
exval = READHSCX(cs, 1, HSCX_EXIR);
exval = hscx_read(bcs, HSCX_EXIR);
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX B EXIR %x", exval);
if (exval & 0x40) {
......@@ -225,7 +224,7 @@ hscx_int_main(struct IsdnCardState *cs, u8 val)
}
if (val & 0x02) {
bcs = cs->bcs;
exval = READHSCX(cs, 0, HSCX_EXIR);
exval = hscx_read(bcs, HSCX_EXIR);
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX A EXIR %x", exval);
if (exval & 0x40) {
......@@ -233,7 +232,8 @@ hscx_int_main(struct IsdnCardState *cs, u8 val)
}
}
if (val & 0x04) {
exval = READHSCX(cs, 0, HSCX_ISTA);
bcs = cs->bcs;
exval = hscx_read(bcs, HSCX_ISTA);
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX A interrupt %x", exval);
hscx_interrupt(cs, exval, 0);
......
......@@ -149,19 +149,6 @@ static struct bc_hw_ops hscx_ops = {
.write_fifo = hscx_write_fifo,
};
#define READHSCX(cs, nr, reg) readreg(cs, \
cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, \
cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs, \
cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs, \
cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
static void
ix1micro_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......
......@@ -139,23 +139,6 @@ static struct bc_hw_ops hscx_ops = {
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs, \
cs->hw.mic.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, \
cs->hw.mic.hscx, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs, \
cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs, \
cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
static void
mic_interrupt(int intno, void *dev_id, struct pt_regs *regs)
......
......@@ -153,24 +153,11 @@ hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
}
static struct bc_hw_ops hscx_ops = {
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
#define READHSCX(cs, nr, reg) readreg(cs->hw.niccy.hscx_ale, \
cs->hw.niccy.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.niccy.hscx_ale, \
cs->hw.niccy.hscx, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.niccy.hscx_ale, \
cs->hw.niccy.hscx, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.niccy.hscx_ale, \
cs->hw.niccy.hscx, (nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
static void
niccy_interrupt(int intno, void *dev_id, struct pt_regs *regs)
......
......@@ -166,17 +166,6 @@ static struct bc_hw_ops hscx_ops = {
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs, cs->hw.teles3.hscx[nr], reg)
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, cs->hw.teles3.hscx[nr], reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
#include "hscx_irq.c"
static void
s0box_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......
......@@ -139,19 +139,6 @@ static struct bc_hw_ops hscx_ops = {
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
#define READHSCX(cs, nr, reg) readreg(cs, \
cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, \
cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs, \
cs->hw.saphir.hscx, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs, \
cs->hw.saphir.hscx, (nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
static void
saphir_interrupt(int intno, void *dev_id, struct pt_regs *regs)
......
......@@ -293,23 +293,6 @@ static struct bc_hw_ops isar_ops = {
.write_reg = isar_write,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs, \
cs->hw.sedl.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, \
cs->hw.sedl.hscx, reg + (nr ? 0x40 : 0), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs, \
cs->hw.sedl.hscx, (nr ? 0x40 : 0), ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs, \
cs->hw.sedl.hscx, (nr ? 0x40 : 0), ptr, cnt)
#include "hscx_irq.c"
static void
sedlbauer_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......
......@@ -111,17 +111,6 @@ static struct bc_hw_ops hscx_ops = {
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) bytein(calc_off(cs->hw.spt.hscx[nr], reg))
#define WRITEHSCX(cs, nr, reg, data) byteout(calc_off(cs->hw.spt.hscx[nr], reg), data)
#define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.spt.hscx[nr], ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.spt.hscx[nr], ptr, cnt)
#include "hscx_irq.c"
static void
sportster_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......
......@@ -110,17 +110,6 @@ static struct bc_hw_ops hscx_ops = {
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) hscx_read(cs, nr, reg)
#define WRITEHSCX(cs, nr, reg, data) hscx_write(cs, nr, reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) hscx_read_fifo(cs, nr, ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) hscx_write_fifo(cs, nr, ptr, cnt)
#include "hscx_irq.c"
static void
teles0_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......
......@@ -113,17 +113,6 @@ static struct bc_hw_ops hscx_ops = {
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.hscx[nr], reg)
#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.hscx[nr], reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.hscxfifo[nr], ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.hscxfifo[nr], ptr, cnt)
#include "hscx_irq.c"
static void
teles3_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......
......@@ -199,17 +199,6 @@ static struct bc_hw_ops hscx_ops = {
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) hscx_read(cs, nr, reg)
#define WRITEHSCX(cs, nr, reg, data) hscx_write(cs, nr, reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) hscx_read_fifo(cs, nr, ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) hscx_write_fifo(cs, nr, ptr, cnt)
#include "hscx_irq.c"
static void
telespci_interrupt(int intno, void *dev_id, struct pt_regs *regs)
{
......
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