Commit 77109411 authored by Bartlomiej Zolnierkiewicz's avatar Bartlomiej Zolnierkiewicz Committed by Eduardo Valentin

thermal: exynos: remove needless triminfo_data abstraction

reg->triminfo_data is used only in exynos_tmu_initialize() and
the code has already different paths for Exynos5440 and other
SoC types (on which TRIMINFO_DATA register offset is identical)
so the register abstraction is not needed and can be removed.

There should be no functional changes caused by this patch.

Cc: Amit Daniel Kachhap <amit.daniel@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Tested-by: default avatarLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: default avatarEduardo Valentin <edubezval@gmail.com>
parent 2251aef6
...@@ -182,22 +182,22 @@ static int exynos_tmu_initialize(struct platform_device *pdev) ...@@ -182,22 +182,22 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
switch (data->id) { switch (data->id) {
case 0: case 0:
trim_info = readl(data->base + trim_info = readl(data->base +
EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data); EXYNOS5440_EFUSE_SWAP_OFFSET + EXYNOS5440_TMU_S0_7_TRIM);
break; break;
case 1: case 1:
trim_info = readl(data->base + reg->triminfo_data); trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
break; break;
case 2: case 2:
trim_info = readl(data->base - trim_info = readl(data->base -
EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data); EXYNOS5440_EFUSE_SWAP_OFFSET + EXYNOS5440_TMU_S0_7_TRIM);
} }
} else { } else {
/* On exynos5420 the triminfo register is in the shared space */ /* On exynos5420 the triminfo register is in the shared space */
if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
trim_info = readl(data->base_second + trim_info = readl(data->base_second +
reg->triminfo_data); EXYNOS_TMU_REG_TRIMINFO);
else else
trim_info = readl(data->base + reg->triminfo_data); trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
} }
data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK; data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
......
...@@ -76,7 +76,6 @@ enum soc_type { ...@@ -76,7 +76,6 @@ enum soc_type {
* struct exynos_tmu_register - register descriptors to access registers and * struct exynos_tmu_register - register descriptors to access registers and
* bitfields. The register validity, offsets and bitfield values may vary * bitfields. The register validity, offsets and bitfield values may vary
* slightly across different exynos SOC's. * slightly across different exynos SOC's.
* @triminfo_data: register containing 2 pont trimming data
* @triminfo_ctrl: trim info controller register. * @triminfo_ctrl: trim info controller register.
* @triminfo_ctrl_count: the number of trim info controller register. * @triminfo_ctrl_count: the number of trim info controller register.
* @tmu_ctrl: TMU main controller register. * @tmu_ctrl: TMU main controller register.
...@@ -107,8 +106,6 @@ enum soc_type { ...@@ -107,8 +106,6 @@ enum soc_type {
* @tmu_pmin: register to get/set the Pmin value. * @tmu_pmin: register to get/set the Pmin value.
*/ */
struct exynos_tmu_registers { struct exynos_tmu_registers {
u32 triminfo_data;
u32 triminfo_ctrl[MAX_TRIMINFO_CTRL_REG]; u32 triminfo_ctrl[MAX_TRIMINFO_CTRL_REG];
u32 triminfo_ctrl_count; u32 triminfo_ctrl_count;
......
...@@ -26,7 +26,6 @@ ...@@ -26,7 +26,6 @@
#if defined(CONFIG_CPU_EXYNOS4210) #if defined(CONFIG_CPU_EXYNOS4210)
static const struct exynos_tmu_registers exynos4210_tmu_registers = { static const struct exynos_tmu_registers exynos4210_tmu_registers = {
.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
.tmu_ctrl = EXYNOS_TMU_REG_CONTROL, .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
.tmu_status = EXYNOS_TMU_REG_STATUS, .tmu_status = EXYNOS_TMU_REG_STATUS,
.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP, .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
...@@ -85,7 +84,6 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = { ...@@ -85,7 +84,6 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
#if defined(CONFIG_SOC_EXYNOS3250) #if defined(CONFIG_SOC_EXYNOS3250)
static const struct exynos_tmu_registers exynos3250_tmu_registers = { static const struct exynos_tmu_registers exynos3250_tmu_registers = {
.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
.triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON1, .triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON1,
.triminfo_ctrl[1] = EXYNOS_TMU_TRIMINFO_CON2, .triminfo_ctrl[1] = EXYNOS_TMU_TRIMINFO_CON2,
.triminfo_ctrl_count = 2, .triminfo_ctrl_count = 2,
...@@ -168,7 +166,6 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = { ...@@ -168,7 +166,6 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
static const struct exynos_tmu_registers exynos4412_tmu_registers = { static const struct exynos_tmu_registers exynos4412_tmu_registers = {
.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
.triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON2, .triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON2,
.triminfo_ctrl_count = 1, .triminfo_ctrl_count = 1,
.tmu_ctrl = EXYNOS_TMU_REG_CONTROL, .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
...@@ -262,7 +259,6 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = { ...@@ -262,7 +259,6 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
#if defined(CONFIG_SOC_EXYNOS5260) #if defined(CONFIG_SOC_EXYNOS5260)
static const struct exynos_tmu_registers exynos5260_tmu_registers = { static const struct exynos_tmu_registers exynos5260_tmu_registers = {
.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
.tmu_ctrl = EXYNOS_TMU_REG_CONTROL, .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT, .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK, .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
...@@ -341,7 +337,6 @@ struct exynos_tmu_init_data const exynos5260_default_tmu_data = { ...@@ -341,7 +337,6 @@ struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
#if defined(CONFIG_SOC_EXYNOS5420) #if defined(CONFIG_SOC_EXYNOS5420)
static const struct exynos_tmu_registers exynos5420_tmu_registers = { static const struct exynos_tmu_registers exynos5420_tmu_registers = {
.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
.tmu_ctrl = EXYNOS_TMU_REG_CONTROL, .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT, .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK, .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
...@@ -428,7 +423,6 @@ struct exynos_tmu_init_data const exynos5420_default_tmu_data = { ...@@ -428,7 +423,6 @@ struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
#if defined(CONFIG_SOC_EXYNOS5440) #if defined(CONFIG_SOC_EXYNOS5440)
static const struct exynos_tmu_registers exynos5440_tmu_registers = { static const struct exynos_tmu_registers exynos5440_tmu_registers = {
.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
.tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL, .tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT, .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK, .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
......
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