Skip to content

L
linux
Commit 782832f2 authored by Yixing Liu's avatar Yixing Liu Committed by Jason Gunthorpe
Browse files
Options

RDMA/hns: Simplify the function config_eqc() 

Use "hr_reg_write" replace "roce_set_filed".

Link: https://lore.kernel.org/r/1617354454-47840-9-git-send-email-liweihang@huawei.comSigned-off-by: default avatarYixing Liu <liuyixing1@huawei.com>
Signed-off-by: default avatarWeihang Li <liweihang@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent 495c2480
Hide whitespace changes
Inline Side-by-side
Showing with 65 additions and 185 deletions
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
View file @ 782832f2
...@@ -6088,6 +6088,16 @@ static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) ...@@ -6088,6 +6088,16 @@ static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
hns_roce_mtr_destroy(hr_dev, &eq->mtr); hns_roce_mtr_destroy(hr_dev, &eq->mtr);
} }
static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
{
eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
eq->cons_index = 0;
eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
eq->shift = ilog2((unsigned int)eq->entries);
}
static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
void *mb_buf) void *mb_buf)
{ {
...@@ -6099,13 +6109,7 @@ static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, ...@@ -6099,13 +6109,7 @@ static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
eqc = mb_buf; eqc = mb_buf;
memset(eqc, 0, sizeof(struct hns_roce_eq_context)); memset(eqc, 0, sizeof(struct hns_roce_eq_context));
/* init eqc */ init_eq_config(hr_dev, eq);
eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
eq->cons_index = 0;
eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
eq->shift = ilog2((unsigned int)eq->entries);
/* if not multi-hop, eqe buffer only use one trunk */ /* if not multi-hop, eqe buffer only use one trunk */
count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
...@@ -6115,102 +6119,34 @@ static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, ...@@ -6115,102 +6119,34 @@ static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
return -ENOBUFS; return -ENOBUFS;
} }
/* set eqc state */ hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID);
roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQ_ST_M, HNS_ROCE_EQC_EQ_ST_S, hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num);
HNS_ROCE_V2_EQ_STATE_VALID); hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore);
hr_reg_write(eqc, EQC_COALESCE, eq->coalesce);
/* set eqe hop num */ hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st);
roce_set_field(eqc->byte_4, HNS_ROCE_EQC_HOP_NUM_M, hr_reg_write(eqc, EQC_EQN, eq->eqn);
HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num); hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT);
hr_reg_write(eqc, EQC_EQE_BA_PG_SZ,
/* set eqc over_ignore */ to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
roce_set_field(eqc->byte_4, HNS_ROCE_EQC_OVER_IGNORE_M, hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ,
HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore); to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX);
/* set eqc coalesce */ hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt);
roce_set_field(eqc->byte_4, HNS_ROCE_EQC_COALESCE_M,
HNS_ROCE_EQC_COALESCE_S, eq->coalesce); hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period);
hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER);
/* set eqc arm_state */ hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3);
roce_set_field(eqc->byte_4, HNS_ROCE_EQC_ARM_ST_M, hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35);
HNS_ROCE_EQC_ARM_ST_S, eq->arm_st); hr_reg_write(eqc, EQC_SHIFT, eq->shift);
hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX);
/* set eqn */ hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12);
roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQN_M, HNS_ROCE_EQC_EQN_S, hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28);
eq->eqn); hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60);
hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX);
/* set eqe_cnt */ hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12);
roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQE_CNT_M, hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44);
HNS_ROCE_EQC_EQE_CNT_S, HNS_ROCE_EQ_INIT_EQE_CNT); hr_reg_write(eqc, EQC_EQE_SIZE,
!!(eq->eqe_size == HNS_ROCE_V3_EQE_SIZE));
/* set eqe_ba_pg_sz */
roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BA_PG_SZ_M,
HNS_ROCE_EQC_BA_PG_SZ_S,
to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
/* set eqe_buf_pg_sz */
roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BUF_PG_SZ_M,
HNS_ROCE_EQC_BUF_PG_SZ_S,
to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
/* set eq_producer_idx */
roce_set_field(eqc->byte_8, HNS_ROCE_EQC_PROD_INDX_M,
HNS_ROCE_EQC_PROD_INDX_S, HNS_ROCE_EQ_INIT_PROD_IDX);
/* set eq_max_cnt */
roce_set_field(eqc->byte_12, HNS_ROCE_EQC_MAX_CNT_M,
HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
/* set eq_period */
roce_set_field(eqc->byte_12, HNS_ROCE_EQC_PERIOD_M,
HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
/* set eqe_report_timer */
roce_set_field(eqc->eqe_report_timer, HNS_ROCE_EQC_REPORT_TIMER_M,
HNS_ROCE_EQC_REPORT_TIMER_S,
HNS_ROCE_EQ_INIT_REPORT_TIMER);
/* set bt_ba [34:3] */
roce_set_field(eqc->eqe_ba0, HNS_ROCE_EQC_EQE_BA_L_M,
HNS_ROCE_EQC_EQE_BA_L_S, bt_ba >> 3);
/* set bt_ba [64:35] */
roce_set_field(eqc->eqe_ba1, HNS_ROCE_EQC_EQE_BA_H_M,
HNS_ROCE_EQC_EQE_BA_H_S, bt_ba >> 35);
/* set eq shift */
roce_set_field(eqc->byte_28, HNS_ROCE_EQC_SHIFT_M, HNS_ROCE_EQC_SHIFT_S,
eq->shift);
/* set eq MSI_IDX */
roce_set_field(eqc->byte_28, HNS_ROCE_EQC_MSI_INDX_M,
HNS_ROCE_EQC_MSI_INDX_S, HNS_ROCE_EQ_INIT_MSI_IDX);
/* set cur_eqe_ba [27:12] */
roce_set_field(eqc->byte_28, HNS_ROCE_EQC_CUR_EQE_BA_L_M,
HNS_ROCE_EQC_CUR_EQE_BA_L_S, eqe_ba[0] >> 12);
/* set cur_eqe_ba [59:28] */
roce_set_field(eqc->byte_32, HNS_ROCE_EQC_CUR_EQE_BA_M_M,
HNS_ROCE_EQC_CUR_EQE_BA_M_S, eqe_ba[0] >> 28);
/* set cur_eqe_ba [63:60] */
roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CUR_EQE_BA_H_M,
HNS_ROCE_EQC_CUR_EQE_BA_H_S, eqe_ba[0] >> 60);
/* set eq consumer idx */
roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M,
HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX);
roce_set_field(eqc->byte_40, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12);
roce_set_field(eqc->byte_44, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44);
roce_set_field(eqc->byte_44, HNS_ROCE_EQC_EQE_SIZE_M,
HNS_ROCE_EQC_EQE_SIZE_S,
eq->eqe_size == HNS_ROCE_V3_EQE_SIZE ? 1 : 0);
return 0; return 0;
} }
......
drivers/infiniband/hw/hns/hns_roce_hw_v2.h
View file @ 782832f2
...@@ -1990,88 +1990,32 @@ struct hns_roce_dip { ...@@ -1990,88 +1990,32 @@ struct hns_roce_dip {
#define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0) #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
#define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0) #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
/* WORD0 */ #define EQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_eq_context, h, l)
#define HNS_ROCE_EQC_EQ_ST_S 0
#define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0) #define EQC_EQ_ST EQC_FIELD_LOC(1, 0)
#define EQC_EQE_HOP_NUM EQC_FIELD_LOC(3, 2)
#define HNS_ROCE_EQC_HOP_NUM_S 2 #define EQC_OVER_IGNORE EQC_FIELD_LOC(4, 4)
#define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2) #define EQC_COALESCE EQC_FIELD_LOC(5, 5)
#define EQC_ARM_ST EQC_FIELD_LOC(7, 6)
#define HNS_ROCE_EQC_OVER_IGNORE_S 4 #define EQC_EQN EQC_FIELD_LOC(15, 8)
#define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4) #define EQC_EQE_CNT EQC_FIELD_LOC(31, 16)
#define EQC_EQE_BA_PG_SZ EQC_FIELD_LOC(35, 32)
#define HNS_ROCE_EQC_COALESCE_S 5 #define EQC_EQE_BUF_PG_SZ EQC_FIELD_LOC(39, 36)
#define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5) #define EQC_EQ_PROD_INDX EQC_FIELD_LOC(63, 40)
#define EQC_EQ_MAX_CNT EQC_FIELD_LOC(79, 64)
#define HNS_ROCE_EQC_ARM_ST_S 6 #define EQC_EQ_PERIOD EQC_FIELD_LOC(95, 80)
#define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6) #define EQC_EQE_REPORT_TIMER EQC_FIELD_LOC(127, 96)
#define EQC_EQE_BA_L EQC_FIELD_LOC(159, 128)
#define HNS_ROCE_EQC_EQN_S 8 #define EQC_EQE_BA_H EQC_FIELD_LOC(188, 160)
#define HNS_ROCE_EQC_EQN_M GENMASK(15, 8) #define EQC_SHIFT EQC_FIELD_LOC(199, 192)
#define EQC_MSI_INDX EQC_FIELD_LOC(207, 200)
#define HNS_ROCE_EQC_EQE_CNT_S 16 #define EQC_CUR_EQE_BA_L EQC_FIELD_LOC(223, 208)
#define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16) #define EQC_CUR_EQE_BA_M EQC_FIELD_LOC(255, 224)
#define EQC_CUR_EQE_BA_H EQC_FIELD_LOC(259, 256)
/* WORD1 */ #define EQC_EQ_CONS_INDX EQC_FIELD_LOC(287, 264)
#define HNS_ROCE_EQC_BA_PG_SZ_S 0 #define EQC_NEX_EQE_BA_L EQC_FIELD_LOC(319, 288)
#define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0) #define EQC_NEX_EQE_BA_H EQC_FIELD_LOC(339, 320)
#define EQC_EQE_SIZE EQC_FIELD_LOC(341, 340)
#define HNS_ROCE_EQC_BUF_PG_SZ_S 4
#define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4)
#define HNS_ROCE_EQC_PROD_INDX_S 8
#define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8)
/* WORD2 */
#define HNS_ROCE_EQC_MAX_CNT_S 0
#define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0)
#define HNS_ROCE_EQC_PERIOD_S 16
#define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16)
/* WORD3 */
#define HNS_ROCE_EQC_REPORT_TIMER_S 0
#define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0)
/* WORD4 */
#define HNS_ROCE_EQC_EQE_BA_L_S 0
#define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0)
/* WORD5 */
#define HNS_ROCE_EQC_EQE_BA_H_S 0
#define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0)
/* WORD6 */
#define HNS_ROCE_EQC_SHIFT_S 0
#define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0)
#define HNS_ROCE_EQC_MSI_INDX_S 8
#define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8)
#define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16
#define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16)
/* WORD7 */
#define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0
#define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0)
/* WORD8 */
#define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0
#define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0)
#define HNS_ROCE_EQC_CONS_INDX_S 8
#define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8)
/* WORD9 */
#define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0
#define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0)
/* WORD10 */
#define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
#define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
#define HNS_ROCE_EQC_EQE_SIZE_S 20
#define HNS_ROCE_EQC_EQE_SIZE_M GENMASK(21, 20)
#define HNS_ROCE_V2_CEQE_COMP_CQN_S 0 #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
#define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0) #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7