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Commit 782f2d78 authored by Cyril Chemparathy's avatar Cyril Chemparathy Committed by Kevin Hilman
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davinci: cleanup mdio arch code and switch to phy_id 

This patch removes davinci architecture code that has now been rendered
useless by the previous patches in the MDIO separation series.

In addition, the earlier phy_mask definitions have been replaced with
corresponding phy_id definitions.
Signed-off-by: default avatarCyril Chemparathy <cyril@ti.com>
Tested-by: default avatarMichael Williamson <michael.williamson@criticallink.com>
Tested-by: default avatarCaglar Akyuz <caglarakyuz@gmail.com>
Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
parent 5d69e007
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Showing with 16 additions and 50 deletions
arch/arm/mach-davinci/board-da830-evm.c
View file @ 782f2d78
...@@ -31,9 +31,7 @@ ...@@ -31,9 +31,7 @@
#include <mach/usb.h> #include <mach/usb.h>
#include <mach/aemif.h> #include <mach/aemif.h>
#define DA830_EVM_PHY_MASK 0x0 #define DA830_EVM_PHY_ID ""
#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
/* /*
* USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4]. * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
*/ */
...@@ -558,9 +556,8 @@ static __init void da830_evm_init(void) ...@@ -558,9 +556,8 @@ static __init void da830_evm_init(void)
da830_evm_usb_init(); da830_evm_usb_init();
soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK;
soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
soc_info->emac_pdata->rmii_en = 1; soc_info->emac_pdata->rmii_en = 1;
soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID;
ret = davinci_cfg_reg_list(da830_cpgmac_pins); ret = davinci_cfg_reg_list(da830_cpgmac_pins);
if (ret) if (ret)
......
arch/arm/mach-davinci/board-da850-evm.c
View file @ 782f2d78
...@@ -38,9 +38,7 @@ ...@@ -38,9 +38,7 @@
#include <mach/mux.h> #include <mach/mux.h>
#include <mach/aemif.h> #include <mach/aemif.h>
#define DA850_EVM_PHY_MASK 0x1 #define DA850_EVM_PHY_ID "0:00"
#define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) #define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) #define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
...@@ -678,8 +676,7 @@ static int __init da850_evm_config_emac(void) ...@@ -678,8 +676,7 @@ static int __init da850_evm_config_emac(void)
/* Enable/Disable MII MDIO clock */ /* Enable/Disable MII MDIO clock */
gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en); gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK; soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID;
soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY;
ret = da8xx_register_emac(); ret = da8xx_register_emac();
if (ret) if (ret)
......
arch/arm/mach-davinci/board-dm365-evm.c
View file @ 782f2d78
...@@ -54,9 +54,7 @@ static inline int have_tvp7002(void) ...@@ -54,9 +54,7 @@ static inline int have_tvp7002(void)
return 0; return 0;
} }
#define DM365_EVM_PHY_MASK (0x2) #define DM365_EVM_PHY_ID "0:01"
#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
/* /*
* A MAX-II CPLD is used for various board control functions. * A MAX-II CPLD is used for various board control functions.
*/ */
...@@ -535,8 +533,7 @@ static void __init evm_init_cpld(void) ...@@ -535,8 +533,7 @@ static void __init evm_init_cpld(void)
/* ... and ENET ... */ /* ... and ENET ... */
dm365evm_emac_configure(); dm365evm_emac_configure();
soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK; soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
resets &= ~BIT(3); resets &= ~BIT(3);
/* ... and AIC33 */ /* ... and AIC33 */
......
arch/arm/mach-davinci/board-dm644x-evm.c
View file @ 782f2d78
...@@ -39,9 +39,7 @@ ...@@ -39,9 +39,7 @@
#include <mach/usb.h> #include <mach/usb.h>
#include <mach/aemif.h> #include <mach/aemif.h>
#define DM644X_EVM_PHY_MASK (0x2) #define DM644X_EVM_PHY_ID "0:01"
#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
#define LXT971_PHY_ID (0x001378e2) #define LXT971_PHY_ID (0x001378e2)
#define LXT971_PHY_MASK (0xfffffff0) #define LXT971_PHY_MASK (0xfffffff0)
...@@ -707,9 +705,7 @@ static __init void davinci_evm_init(void) ...@@ -707,9 +705,7 @@ static __init void davinci_evm_init(void)
davinci_serial_init(&uart_config); davinci_serial_init(&uart_config);
dm644x_init_asp(&dm644x_evm_snd_data); dm644x_init_asp(&dm644x_evm_snd_data);
soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK; soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY;
/* Register the fixup for PHY on DaVinci */ /* Register the fixup for PHY on DaVinci */
phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
davinci_phy_fixup); davinci_phy_fixup);
......
arch/arm/mach-davinci/board-dm646x-evm.c
View file @ 782f2d78
...@@ -729,9 +729,7 @@ static struct davinci_uart_config uart_config __initdata = { ...@@ -729,9 +729,7 @@ static struct davinci_uart_config uart_config __initdata = {
.enabled_uarts = (1 << 0), .enabled_uarts = (1 << 0),
}; };
#define DM646X_EVM_PHY_MASK (0x2) #define DM646X_EVM_PHY_ID "0:01"
#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
/* /*
* The following EDMA channels/slots are not being used by drivers (for * The following EDMA channels/slots are not being used by drivers (for
* example: Timer, GPIO, UART events etc) on dm646x, hence they are being * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
...@@ -784,8 +782,7 @@ static __init void evm_init(void) ...@@ -784,8 +782,7 @@ static __init void evm_init(void)
if (HAS_ATA) if (HAS_ATA)
davinci_init_ide(); davinci_init_ide();
soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
} }
#define DM646X_EVM_REF_FREQ 27000000 #define DM646X_EVM_REF_FREQ 27000000
......
arch/arm/mach-davinci/board-mityomapl138.c
View file @ 782f2d78
...@@ -24,9 +24,7 @@ ...@@ -24,9 +24,7 @@
#include <mach/nand.h> #include <mach/nand.h>
#include <mach/mux.h> #include <mach/mux.h>
#define MITYOMAPL138_PHY_MASK 0x08 /* hardcoded for now */ #define MITYOMAPL138_PHY_ID "0:03"
#define MITYOMAPL138_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
.bus_freq = 100, /* kHz */ .bus_freq = 100, /* kHz */
.bus_delay = 0, /* usec */ .bus_delay = 0, /* usec */
...@@ -273,9 +271,7 @@ static void __init mityomapl138_config_emac(void) ...@@ -273,9 +271,7 @@ static void __init mityomapl138_config_emac(void)
/* configure the CFGCHIP3 register for RMII or MII */ /* configure the CFGCHIP3 register for RMII or MII */
__raw_writel(val, cfg_chip3_base); __raw_writel(val, cfg_chip3_base);
soc_info->emac_pdata->phy_mask = MITYOMAPL138_PHY_MASK; soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
pr_debug("setting phy_mask to %x\n", soc_info->emac_pdata->phy_mask);
soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY;
ret = da8xx_register_emac(); ret = da8xx_register_emac();
if (ret) if (ret)
......
arch/arm/mach-davinci/board-neuros-osd2.c
View file @ 782f2d78
...@@ -39,9 +39,7 @@ ...@@ -39,9 +39,7 @@
#include <mach/mmc.h> #include <mach/mmc.h>
#include <mach/usb.h> #include <mach/usb.h>
#define NEUROS_OSD2_PHY_MASK 0x2 #define NEUROS_OSD2_PHY_ID "0:01"
#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
#define LXT971_PHY_ID 0x001378e2 #define LXT971_PHY_ID 0x001378e2
#define LXT971_PHY_MASK 0xfffffff0 #define LXT971_PHY_MASK 0xfffffff0
...@@ -252,8 +250,7 @@ static __init void davinci_ntosd2_init(void) ...@@ -252,8 +250,7 @@ static __init void davinci_ntosd2_init(void)
davinci_serial_init(&uart_config); davinci_serial_init(&uart_config);
dm644x_init_asp(&dm644x_ntosd2_snd_data); dm644x_init_asp(&dm644x_ntosd2_snd_data);
soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK; soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;
davinci_setup_usb(1000, 8); davinci_setup_usb(1000, 8);
/* /*
......
arch/arm/mach-davinci/board-sffsdr.c
View file @ 782f2d78
...@@ -42,9 +42,7 @@ ...@@ -42,9 +42,7 @@
#include <mach/mux.h> #include <mach/mux.h>
#include <mach/usb.h> #include <mach/usb.h>
#define SFFSDR_PHY_MASK (0x2) #define SFFSDR_PHY_ID "0:01"
#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
static struct mtd_partition davinci_sffsdr_nandflash_partition[] = { static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
/* U-Boot Environment: Block 0 /* U-Boot Environment: Block 0
* UBL: Block 1 * UBL: Block 1
...@@ -143,8 +141,7 @@ static __init void davinci_sffsdr_init(void) ...@@ -143,8 +141,7 @@ static __init void davinci_sffsdr_init(void)
ARRAY_SIZE(davinci_sffsdr_devices)); ARRAY_SIZE(davinci_sffsdr_devices));
sffsdr_init_i2c(); sffsdr_init_i2c();
davinci_serial_init(&uart_config); davinci_serial_init(&uart_config);
soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK; soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID;
soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY;
davinci_setup_usb(0, 0); /* We support only peripheral mode. */ davinci_setup_usb(0, 0); /* We support only peripheral mode. */
/* mux VLYNQ pins */ /* mux VLYNQ pins */
......
arch/arm/mach-davinci/devices-da8xx.c
View file @ 782f2d78
...@@ -42,7 +42,6 @@ ...@@ -42,7 +42,6 @@
#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
#define DA8XX_EMAC_RAM_OFFSET 0x0000 #define DA8XX_EMAC_RAM_OFFSET 0x0000
#define DA8XX_MDIO_REG_OFFSET 0x4000
#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
void __iomem *da8xx_syscfg0_base; void __iomem *da8xx_syscfg0_base;
...@@ -381,7 +380,6 @@ struct emac_platform_data da8xx_emac_pdata = { ...@@ -381,7 +380,6 @@ struct emac_platform_data da8xx_emac_pdata = {
.ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
.ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
.ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
.mdio_reg_offset = DA8XX_MDIO_REG_OFFSET,
.ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
.version = EMAC_VERSION_2, .version = EMAC_VERSION_2,
}; };
......
arch/arm/mach-davinci/dm365.c
View file @ 782f2d78
...@@ -691,7 +691,6 @@ static struct emac_platform_data dm365_emac_pdata = { ...@@ -691,7 +691,6 @@ static struct emac_platform_data dm365_emac_pdata = {
.ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
.ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
.ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET, .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
.mdio_reg_offset = DM365_EMAC_MDIO_OFFSET,
.ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE, .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
.version = EMAC_VERSION_2, .version = EMAC_VERSION_2,
}; };
......
arch/arm/mach-davinci/dm644x.c
View file @ 782f2d78
...@@ -322,7 +322,6 @@ static struct emac_platform_data dm644x_emac_pdata = { ...@@ -322,7 +322,6 @@ static struct emac_platform_data dm644x_emac_pdata = {
.ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
.ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET, .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
.ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET, .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
.mdio_reg_offset = DM644X_EMAC_MDIO_OFFSET,
.ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE, .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
.version = EMAC_VERSION_1, .version = EMAC_VERSION_1,
}; };
......
arch/arm/mach-davinci/dm646x.c
View file @ 782f2d78
...@@ -358,7 +358,6 @@ static struct emac_platform_data dm646x_emac_pdata = { ...@@ -358,7 +358,6 @@ static struct emac_platform_data dm646x_emac_pdata = {
.ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
.ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET, .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
.ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET, .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
.mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET,
.ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE, .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
.version = EMAC_VERSION_2, .version = EMAC_VERSION_2,
}; };
......
arch/arm/mach-davinci/include/mach/dm365.h
View file @ 782f2d78
...@@ -25,7 +25,6 @@ ...@@ -25,7 +25,6 @@
#define DM365_EMAC_CNTRL_OFFSET (0x0000) #define DM365_EMAC_CNTRL_OFFSET (0x0000)
#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) #define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000)
#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) #define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000)
#define DM365_EMAC_MDIO_OFFSET (0x4000)
#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) #define DM365_EMAC_CNTRL_RAM_SIZE (0x2000)
/* Base of key scan register bank */ /* Base of key scan register bank */
......
arch/arm/mach-davinci/include/mach/dm644x.h
View file @ 782f2d78
...@@ -32,7 +32,6 @@ ...@@ -32,7 +32,6 @@
#define DM644X_EMAC_CNTRL_OFFSET (0x0000) #define DM644X_EMAC_CNTRL_OFFSET (0x0000)
#define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000) #define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000)
#define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000) #define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000)
#define DM644X_EMAC_MDIO_OFFSET (0x4000)
#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) #define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000 #define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000
......
arch/arm/mach-davinci/include/mach/dm646x.h
View file @ 782f2d78
...@@ -23,7 +23,6 @@ ...@@ -23,7 +23,6 @@
#define DM646X_EMAC_CNTRL_OFFSET (0x0000) #define DM646X_EMAC_CNTRL_OFFSET (0x0000)
#define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000) #define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000)
#define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000) #define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000)
#define DM646X_EMAC_MDIO_OFFSET (0x4000)
#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) #define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000 #define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
......
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