Commit 78ad6864 authored by Carlos Song's avatar Carlos Song Committed by Jonathan Cameron

iio: imu: fxos8700: fix incorrect ODR mode readback

The absence of a correct offset leads an incorrect ODR mode
readback after use a hexadecimal number to mark the value from
FXOS8700_CTRL_REG1.

Get ODR mode by field mask and FIELD_GET clearly and conveniently.
And attach other additional fix for keeping the original code logic
and a good readability.

Fixes: 84e5ddd5 ("iio: imu: Add support for the FXOS8700 IMU")
Signed-off-by: default avatarCarlos Song <carlos.song@nxp.com>
Link: https://lore.kernel.org/r/20230118074227.1665098-2-carlos.song@nxp.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
parent ee3c5b64
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/acpi.h> #include <linux/acpi.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include <linux/bitfield.h>
#include <linux/iio/iio.h> #include <linux/iio/iio.h>
#include <linux/iio/sysfs.h> #include <linux/iio/sysfs.h>
...@@ -144,9 +145,9 @@ ...@@ -144,9 +145,9 @@
#define FXOS8700_NVM_DATA_BNK0 0xa7 #define FXOS8700_NVM_DATA_BNK0 0xa7
/* Bit definitions for FXOS8700_CTRL_REG1 */ /* Bit definitions for FXOS8700_CTRL_REG1 */
#define FXOS8700_CTRL_ODR_MSK 0x38
#define FXOS8700_CTRL_ODR_MAX 0x00 #define FXOS8700_CTRL_ODR_MAX 0x00
#define FXOS8700_CTRL_ODR_MIN GENMASK(4, 3) #define FXOS8700_CTRL_ODR_MIN GENMASK(4, 3)
#define FXOS8700_CTRL_ODR_MSK GENMASK(5, 3)
/* Bit definitions for FXOS8700_M_CTRL_REG1 */ /* Bit definitions for FXOS8700_M_CTRL_REG1 */
#define FXOS8700_HMS_MASK GENMASK(1, 0) #define FXOS8700_HMS_MASK GENMASK(1, 0)
...@@ -508,10 +509,9 @@ static int fxos8700_set_odr(struct fxos8700_data *data, enum fxos8700_sensor t, ...@@ -508,10 +509,9 @@ static int fxos8700_set_odr(struct fxos8700_data *data, enum fxos8700_sensor t,
if (i >= odr_num) if (i >= odr_num)
return -EINVAL; return -EINVAL;
return regmap_update_bits(data->regmap, val &= ~FXOS8700_CTRL_ODR_MSK;
FXOS8700_CTRL_REG1, val |= FIELD_PREP(FXOS8700_CTRL_ODR_MSK, fxos8700_odr[i].bits) | FXOS8700_ACTIVE;
FXOS8700_CTRL_ODR_MSK + FXOS8700_ACTIVE, return regmap_write(data->regmap, FXOS8700_CTRL_REG1, val);
fxos8700_odr[i].bits << 3 | active_mode);
} }
static int fxos8700_get_odr(struct fxos8700_data *data, enum fxos8700_sensor t, static int fxos8700_get_odr(struct fxos8700_data *data, enum fxos8700_sensor t,
...@@ -524,7 +524,7 @@ static int fxos8700_get_odr(struct fxos8700_data *data, enum fxos8700_sensor t, ...@@ -524,7 +524,7 @@ static int fxos8700_get_odr(struct fxos8700_data *data, enum fxos8700_sensor t,
if (ret) if (ret)
return ret; return ret;
val &= FXOS8700_CTRL_ODR_MSK; val = FIELD_GET(FXOS8700_CTRL_ODR_MSK, val);
for (i = 0; i < odr_num; i++) for (i = 0; i < odr_num; i++)
if (val == fxos8700_odr[i].bits) if (val == fxos8700_odr[i].bits)
......
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