Commit 791a9e00 authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard

arm64: allwinner: a64: add r_ccu node

A64 SoC have a CCU (r_ccu) in PRCM block.

Add the device node for it.

The mux 3 of R_CCU is an internal oscillator, which is 16MHz according
to the user manual, and has only 30% accuracy based on our experience
on older SoCs. The real mesaured value of it on two Pine64 boards is
around 11MHz, which is around 70% of 16MHz.
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent c1ae3cfa
...@@ -98,6 +98,14 @@ osc32k: osc32k_clk { ...@@ -98,6 +98,14 @@ osc32k: osc32k_clk {
clock-output-names = "osc32k"; clock-output-names = "osc32k";
}; };
iosc: internal-osc-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16000000>;
clock-accuracy = <300000000>;
clock-output-names = "iosc";
};
psci { psci {
compatible = "arm,psci-0.2"; compatible = "arm,psci-0.2";
method = "smc"; method = "smc";
...@@ -392,5 +400,14 @@ rtc: rtc@1f00000 { ...@@ -392,5 +400,14 @@ rtc: rtc@1f00000 {
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
}; };
r_ccu: clock@1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
clocks = <&osc24M>, <&osc32k>, <&iosc>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
}; };
}; };
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