Commit 791b0ade authored by Antoine Tenart's avatar Antoine Tenart Committed by Gregory CLEMENT

arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node

The network driver on Marvell SoC (7k/8k) needs to access some registers
in the system controller to configure its ports at runtime. This patch
adds a phandle reference to the syscon system controller node in the
ppv2 node.
Signed-off-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Tested-by: default avatarMarcin Wojtas <mw@semihalf.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 2c90e365
...@@ -65,6 +65,7 @@ cpm_ethernet: ethernet@0 { ...@@ -65,6 +65,7 @@ cpm_ethernet: ethernet@0 {
reg = <0x0 0x100000>, <0x129000 0xb000>; reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>; clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk"; clock-names = "pp_clk", "gop_clk", "mg_clk";
marvell,system-controller = <&cpm_syscon0>;
status = "disabled"; status = "disabled";
dma-coherent; dma-coherent;
......
...@@ -65,6 +65,7 @@ cps_ethernet: ethernet@0 { ...@@ -65,6 +65,7 @@ cps_ethernet: ethernet@0 {
reg = <0x0 0x100000>, <0x129000 0xb000>; reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>; clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk"; clock-names = "pp_clk", "gop_clk", "mg_clk";
marvell,system-controller = <&cps_syscon0>;
status = "disabled"; status = "disabled";
dma-coherent; dma-coherent;
......
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