Commit 796705bc authored by Sowjanya Komatineni's avatar Sowjanya Komatineni Committed by Thierry Reding

dt-bindings: clock: tegra: Add clock ID for CSI TPG clock

Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock
ID for this CSI TPG clock from PLLD.
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 8f3d9f35
...@@ -358,7 +358,7 @@ ...@@ -358,7 +358,7 @@
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
/* 325 */ /* 325 */
#define TEGRA210_CLK_OSC 326 #define TEGRA210_CLK_OSC 326
/* 327 */ #define TEGRA210_CLK_CSI_TPG 327
/* 328 */ /* 328 */
/* 329 */ /* 329 */
/* 330 */ /* 330 */
......
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