Commit 79c23081 authored by Alex He's avatar Alex He Committed by Willy Tarreau

xHCI: Correct the #define XHCI_LEGACY_DISABLE_SMI

commit 95018a53 upstream.

Re-define XHCI_LEGACY_DISABLE_SMI and used it in right way. All SMI enable
bits will be cleared to zero and flag bits 29:31 are also cleared to zero.
Other bits should be presvered as Table 146.

This patch should be backported to kernels as old as 2.6.31.
Signed-off-by: default avatarAlex He <alex.he@amd.com>
Signed-off-by: default avatarSarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarWilly Tarreau <w@1wt.eu>
parent 737b15bb
...@@ -458,9 +458,13 @@ static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev) ...@@ -458,9 +458,13 @@ static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
} }
} }
/* Disable any BIOS SMIs */ val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
writel(XHCI_LEGACY_DISABLE_SMI, /* Mask off (turn off) any enabled SMIs */
base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); val &= XHCI_LEGACY_DISABLE_SMI;
/* Mask all SMI events bits, RW1C */
val |= XHCI_LEGACY_SMI_EVENTS;
/* Disable any BIOS SMIs and clear all SMI events*/
writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
hc_init: hc_init:
op_reg_base = base + XHCI_HC_LENGTH(readl(base)); op_reg_base = base + XHCI_HC_LENGTH(readl(base));
......
...@@ -62,8 +62,9 @@ ...@@ -62,8 +62,9 @@
/* USB Legacy Support Control and Status Register - section 7.1.2 */ /* USB Legacy Support Control and Status Register - section 7.1.2 */
/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
#define XHCI_LEGACY_CONTROL_OFFSET (0x04) #define XHCI_LEGACY_CONTROL_OFFSET (0x04)
/* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ /* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
#define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) #define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17))
#define XHCI_LEGACY_SMI_EVENTS (0x7 << 29)
/* command register values to disable interrupts and halt the HC */ /* command register values to disable interrupts and halt the HC */
/* start/stop HC execution - do not write unless HC is halted*/ /* start/stop HC execution - do not write unless HC is halted*/
......
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