Commit 79c81530 authored by Alex Hung's avatar Alex Hung Committed by Alex Deucher

Revert "drm/amd/display: Add writeback enable/disable in dc"

This reverts commit c6d3c7b6.

[WHY & HOW]
The writeback series cause a regression in thunderbolt display.
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c1929159
......@@ -467,25 +467,6 @@ bool dc_stream_add_writeback(struct dc *dc,
struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
dwb->otg_inst = stream_status->primary_otg_inst;
}
if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
dm_error("DC: update_bandwidth failed!\n");
return false;
}
/* enable writeback */
if (dc->hwss.enable_writeback) {
struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
if (dwb->funcs->is_enabled(dwb)) {
/* writeback pipe already enabled, only need to update */
dc->hwss.update_writeback(dc, wb_info, dc->current_state);
} else {
/* Enable writeback pipe from scratch*/
dc->hwss.enable_writeback(dc, wb_info, dc->current_state);
}
}
return true;
}
......@@ -530,20 +511,6 @@ bool dc_stream_remove_writeback(struct dc *dc,
}
stream->num_wb_info = j;
/* recalculate and apply DML parameters */
if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
dm_error("DC: update_bandwidth failed!\n");
return false;
}
/* disable writeback */
if (dc->hwss.disable_writeback) {
struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];
if (dwb->funcs->is_enabled(dwb))
dc->hwss.disable_writeback(dc, dwb_pipe_inst);
}
return true;
}
......
......@@ -367,10 +367,6 @@ void dcn30_enable_writeback(
DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
__func__, wb_info->dwb_pipe_inst,\
wb_info->mpcc_inst);
/* Warmup interface */
dcn30_mmhubbub_warmup(dc, 1, wb_info);
/* Update writeback pipe */
dcn30_set_writeback(dc, wb_info, context);
......
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