Commit 7acece71 authored by Chris Brandt's avatar Chris Brandt Committed by Greg Kroah-Hartman

serial: sh-sci: Remove SCIx_RZ_SCIFA_REGTYPE

There is no more need for SCIx_RZ_SCIFA_REGTYPE now that
SCIx_SH4_SCIF_REGTYPE can provide the same register/address definitions.

Also, R7S9210 no longer needs a special compatible since the standard
"renesas,scif" will work just fine.
Signed-off-by: default avatarChris Brandt <chris.brandt@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 2d4dd0da
...@@ -293,33 +293,6 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { ...@@ -293,33 +293,6 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
.error_clear = SCIF_ERROR_CLEAR, .error_clear = SCIF_ERROR_CLEAR,
}, },
/*
* The "SCIFA" that is in RZ/T and RZ/A2.
* It looks like a normal SCIF with FIFO data, but with a
* compressed address space. Also, the break out of interrupts
* are different: ERI/BRI, RXI, TXI, TEI, DRI.
*/
[SCIx_RZ_SCIFA_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
[SCBRR] = { 0x02, 8 },
[SCSCR] = { 0x04, 16 },
[SCxTDR] = { 0x06, 8 },
[SCxSR] = { 0x08, 16 },
[SCxRDR] = { 0x0A, 8 },
[SCFCR] = { 0x0C, 16 },
[SCFDR] = { 0x0E, 16 },
[SCSPTR] = { 0x10, 16 },
[SCLSR] = { 0x12, 16 },
},
.fifosize = 16,
.overrun_reg = SCLSR,
.overrun_mask = SCLSR_ORER,
.sampling_rate_mask = SCI_SR(32),
.error_mask = SCIF_DEFAULT_ERROR_MASK,
.error_clear = SCIF_ERROR_CLEAR,
},
/* /*
* Common SH-3 SCIF definitions. * Common SH-3 SCIF definitions.
*/ */
...@@ -3148,10 +3121,6 @@ static const struct of_device_id of_sci_match[] = { ...@@ -3148,10 +3121,6 @@ static const struct of_device_id of_sci_match[] = {
.compatible = "renesas,scif-r7s72100", .compatible = "renesas,scif-r7s72100",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
}, },
{
.compatible = "renesas,scif-r7s9210",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
},
/* Family-specific types */ /* Family-specific types */
{ {
.compatible = "renesas,rcar-gen1-scif", .compatible = "renesas,rcar-gen1-scif",
......
...@@ -36,7 +36,6 @@ enum { ...@@ -36,7 +36,6 @@ enum {
SCIx_SH4_SCIF_FIFODATA_REGTYPE, SCIx_SH4_SCIF_FIFODATA_REGTYPE,
SCIx_SH7705_SCIF_REGTYPE, SCIx_SH7705_SCIF_REGTYPE,
SCIx_HSCIF_REGTYPE, SCIx_HSCIF_REGTYPE,
SCIx_RZ_SCIFA_REGTYPE,
SCIx_NR_REGTYPES, SCIx_NR_REGTYPES,
}; };
......
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