Commit 7add905f authored by Eilon Greenstein's avatar Eilon Greenstein Committed by David S. Miller

bnx2x: Fan failure mechanism on additional design

The A1021G board is also using the fan failure mechanism in the same way
the A1022G board does
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2772f903
...@@ -2550,6 +2550,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) ...@@ -2550,6 +2550,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
BNX2X_ERR("SPIO5 hw attention\n"); BNX2X_ERR("SPIO5 hw attention\n");
switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) { switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
/* Fan failure attention */ /* Fan failure attention */
...@@ -5337,6 +5338,7 @@ static int bnx2x_init_common(struct bnx2x *bp) ...@@ -5337,6 +5338,7 @@ static int bnx2x_init_common(struct bnx2x *bp)
} }
switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) { switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
/* Fan failure is indicated by SPIO 5 */ /* Fan failure is indicated by SPIO 5 */
bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
...@@ -5531,6 +5533,7 @@ static int bnx2x_init_port(struct bnx2x *bp) ...@@ -5531,6 +5533,7 @@ static int bnx2x_init_port(struct bnx2x *bp)
/* Port DMAE comes here */ /* Port DMAE comes here */
switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) { switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
/* add SPIO 5 to group 0 */ /* add SPIO 5 to group 0 */
val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
......
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