Commit 7b2e1de8 authored by Chun-Jie Chen's avatar Chun-Jie Chen Committed by Stephen Boyd

clk: mediatek: Add MT8195 ccusys clock support

Add MT8195 ccusys clock controller which provides clock gate
control in Camera Computing Unit.
Signed-off-by: default avatarChun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-12-chun-jie.chen@mediatek.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 9d0c6572
...@@ -82,6 +82,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o ...@@ -82,6 +82,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o \ obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o \
clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o \ clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o \
clk-mt8195-cam.o clk-mt8195-cam.o clk-mt8195-ccu.o
obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs ccu_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_CCU(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate ccu_clks[] = {
GATE_CCU(CLK_CCU_LARB18, "ccu_larb18", "top_ccu", 0),
GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "top_ccu", 1),
GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "top_ccu", 2),
GATE_CCU(CLK_CCU_CCU1, "ccu_ccu1", "top_ccu", 3),
};
static const struct mtk_clk_desc ccu_desc = {
.clks = ccu_clks,
.num_clks = ARRAY_SIZE(ccu_clks),
};
static const struct of_device_id of_match_clk_mt8195_ccu[] = {
{
.compatible = "mediatek,mt8195-ccusys",
.data = &ccu_desc,
}, {
/* sentinel */
}
};
static struct platform_driver clk_mt8195_ccu_drv = {
.probe = mtk_clk_simple_probe,
.driver = {
.name = "clk-mt8195-ccu",
.of_match_table = of_match_clk_mt8195_ccu,
},
};
builtin_platform_driver(clk_mt8195_ccu_drv);
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