Commit 7b827835 authored by Aristeu Rozanski's avatar Aristeu Rozanski Committed by Mauro Carvalho Chehab

edac: add DDR4 and RDDR4

Haswell memory controller can make use of DDR4 and Registered DDR4

Cc: tony.luck@intel.com
Signed-off-by: default avatarAristeu Rozanski <aris@redhat.com>
Signed-off-by: default avatarMauro Carvalho Chehab <m.chehab@samsung.com>
parent adc61bcd
...@@ -108,7 +108,9 @@ static const char * const mem_types[] = { ...@@ -108,7 +108,9 @@ static const char * const mem_types[] = {
[MEM_RDDR2] = "Registered-DDR2", [MEM_RDDR2] = "Registered-DDR2",
[MEM_XDR] = "XDR", [MEM_XDR] = "XDR",
[MEM_DDR3] = "Unbuffered-DDR3", [MEM_DDR3] = "Unbuffered-DDR3",
[MEM_RDDR3] = "Registered-DDR3" [MEM_RDDR3] = "Registered-DDR3",
[MEM_DDR4] = "Unbuffered-DDR4",
[MEM_RDDR4] = "Registered-DDR4"
}; };
static const char * const dev_types[] = { static const char * const dev_types[] = {
......
...@@ -194,6 +194,9 @@ static inline char *mc_event_error_type(const unsigned int err_type) ...@@ -194,6 +194,9 @@ static inline char *mc_event_error_type(const unsigned int err_type)
* @MEM_DDR3: DDR3 RAM * @MEM_DDR3: DDR3 RAM
* @MEM_RDDR3: Registered DDR3 RAM * @MEM_RDDR3: Registered DDR3 RAM
* This is a variant of the DDR3 memories. * This is a variant of the DDR3 memories.
* @MEM_DDR4: DDR4 RAM
* @MEM_RDDR4: Registered DDR4 RAM
* This is a variant of the DDR4 memories.
*/ */
enum mem_type { enum mem_type {
MEM_EMPTY = 0, MEM_EMPTY = 0,
...@@ -213,6 +216,8 @@ enum mem_type { ...@@ -213,6 +216,8 @@ enum mem_type {
MEM_XDR, MEM_XDR,
MEM_DDR3, MEM_DDR3,
MEM_RDDR3, MEM_RDDR3,
MEM_DDR4,
MEM_RDDR4,
}; };
#define MEM_FLAG_EMPTY BIT(MEM_EMPTY) #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
......
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